Floating-Point Unit (FPU)

The Floating-Point Unit is an optional part of the SPARC processor. As its name suggests, the FPU handles all floating-point operations and arithmetic. Like the Integer Unit, the FPU has a set of working data registers, a control and status register, and an optional deferred-trap queue.

Floating-point instructions and data formats, as defined by the SPARC Version 8 Specification, conform to the ANSI/IEEE Standard 754-1985. However, the SPARC specification doesn't require that all aspects of the ANSI/IEEE standard be implemented in the SPARC hardware. In cases where the hardware implementation does not meet the ANSI/IEEE standard, an exception trap may be generated and the operating system software performs the necessary work instead.

Since the Floating-Point Unit is optional, the operating system must be able to completely and properly provide the user with precisely the exact results that the FPU would have provided, as according to the ANSI/IEEE standard. The user needn't worry about whether an FPU exists on his system. When an FPU is available, the Integer Unit will just pass all the floating-point instructions over to it for execution. This means the FPU will be operating in parallel with the IU.

If the FPU doesn't exist in a SPARC processor, or if the enable floating-point EF bit in the PSR is set to 0 and a floating-point instruction is executed, an fp_disabled trap will occur. Again, in this case, the operating system intervenes and performs the floating-point operation via software instead of via hardware.

As you can probably imagine, performing all floating-point operations on an FPU instead of via software can make a huge performance difference. FPU performance is often measured in units of megaflops, or millions of floating-point operations per second.

FPU F Registers

The FPU has thirty-two 32-bit floating-point working data registers, known as f registers. The f registers can be used to represent 32 single-precision, 16 double-precision, or 8 quad-precision floating-point values at a given time, or combinations of these. Unlike the windowed IU general purpose registers, all 32 f registers can be accessed by a routine at any time.

Floating-point State Register

Like the IU, the FPU has a status and control register. We won't be using this register very often during system crash dump analysis, so we will only introduce you to it. For complete technical information about the FSR and the contents of some of its fields, refer to both the SPARC Version 8 Specification and the ANSI/IEEE Standard 754-1985, preferably on nights when you can't sleep. The register fields and their bit assignments are diagrammed below.

Figure A-4. FPU status and control register

The RD field selects the "rounding direction" for floating-point results.

Bits 29, 28, and 12 are currently undefined in the SPARC Version 8 Specification.

The TEM field contains the Trap Enable Mask. Each bit represents a different exception type that may be generated by floating-point operations. If the bit is set, the exception will generate a trap. We will list the possible exceptions shortly.

The NS bit, when set, allows the FPU to produce nonstandard results, that is, results that may not meet the ANSI/IEEE Standard 765-1985.

Bits 21 and 20 are reserved for future use.

The ver field contains the FPU implementation version number.

The ftt field is used to identify floating-point exception trap types.

The qne bit is set if there is an optional floating-point deferred-trap queue (FQ) and it is not empty.

The fcc field is the FPU's equivalent to the IU's icc field in the PSR . The two bits are used to represent different floating-point relationships, which are recorded when working with two floating-point values. They are as follows :

Table A-1. FPU fcc bits

fcc bits	Relationship Between Two Floating-point Values
00	f 1 = f 2	Values were equal
01	f 1 < f 2	f1 less than f2
10	f 1 > f 2	f1 greater than f2
11	f 1 ? f 2	f1 and f2 are unordered

The aexc and cexc fields are used to record the accumulated exceptions and the current exceptions generated by floating-point operations. The five bits of each of these fields correspond to the five bits of the TEM field. Starting with the high-order bit, they are:

• NV ” Invalid operation

• OF ” Overflow

• UF ” Underflow

• DZ ” Divide by zero

• NX ” Rounded result differs from exact correct result

Floating-point deferred-trap queue (FQ)

Like the Integer Unit, the Floating-Point Unit can optionally be implemented to include a floating-point deferred-trap queue. If a deferred-trap queue does not exist on the FPU, the FSR qne bit will be set to 0. The contents and operations of the FQ are completely implementation dependent.