Integer Unit (IU)

The Integer Unit is really the heart of the SPARC processor; the central processing unit, if you prefer. The IU controls the overall operation of the processor. It loads and controls the execution of program instructions, calculates memory addresses, and has an arithmetic and logic unit (ALU).

The IU also owns the registers we will be referencing most often during system crash dump analysis, as well as a few we may never use. All of the IU registers are 32 bits wide. Let's discuss each of them.

General-purpose registers

According to the SPARC Version 8 specification, there may be anywhere from 40 to 520 general-purpose registers. These are also referred to as working data registers. These are the registers used to transfer data between memory and the processor or to hold results of operations performed in the IU.

SPARC general-purpose registers are viewed in groups or clusters known as windows . We'll be discussing the concept of windows a little later in this appendix. Another discussion, in more detail, can be found in Chapter 17, "Stacks."

PC ” Program Counter

The Program Counter contains the address of the instruction currently being executed by the integer unit.

nPC ” next Program Counter

As its name suggests, the nPC contains the address of the next instruction expected to be executed by the IU.

When a delayed control transfer instruction is executed, nPC will point to the target of the instruction. This might not mean much to you right now, but it will as soon as we start talking, in Appendix B, about the different instructions available on the SPARC processor.

PSR ” Processor Status Register

The PSR contains useful information regarding, as the name implies, the status of the processor. Let's look at the Processor Status Register bit by bit. We point out the nibble boundaries because you'll be looking at this register in hexadecimal, and each hex digit represents one nibble (half a byte)

Figure A-2. Process Status Register bits

The impl and vers fields, implementation and version, are hardwired by the processor manufacture to identify the processor chip and its revision level.

The icc field, Integer Condition Codes, is used by the arithmetic logic unit to record conditions caused by the arithmetic and logic instructions whose names end in cc . There are four bits in the icc field, one for each of the following conditions:

Bit 23	Condition n, n egative result occurred
Bit 22	Condition z, result was z ero
Bit 21	Condition v, o v erflow occurred
Bit 20	Condition c, bit 31 was c arried or borrowed

The EC and EF fields, Enable Coprocessor and Enable Floating-point unit, are set accordingly when these optional pieces of hardware are available for use. If a unit is not enabled and an instruction tries to access the unit, a trap will occur.

The PIL field of the Processor Status Register identifies the Processor Interrupt Level above which the processor will accept an interrupt. Interrupt level 15 is the highest possible interrupt on this architecture; thus, only 4 bits are needed for the PIL field.

The S field is set to 1 when the processor is running in Supervisor mode, 0 when running in user mode. In user mode, certain privileged instructions cannot be executed. The S bit can only be set by the hardware and is set whenever a trap occurs. Once the bit set, the operating system clears it when Supervisor mode is no longer needed. Essentially, this is done on return to a user program.

The PS field contains the value of the S bit at the time of the most recent trap ” the previous S bit. Examining this flag will allow the kernel to identify when a trap was issued from a user program or from kernel code.

The ET field of the Processor Status Register is set to 1 when Traps are Enabled. When set to 0, traps are ignored.

The CWP field is the Current Window Pointer and identifies which register window is in use. This SPARC implementation allows up to 32 register windows, numbered 0 to 31, thus, only 5 bits are needed for the CWP.

TBR ” Trap Base Register

The TBR contains three fields that, when concatenated , become a valid memory address pointing to where control is transferred when a trap occurs. The TBR is diagrammed below.

Figure A-3. Trap Base Register bits

Here's a rare example of when TBA does not mean "To Be Announced." The TBA field contains the Trap Base Address. This will be the most significant 20 bits of the trap vector table address.

The 8-bit-wide tt, or trap type field, is written by the hardware when a trap occurs. It provides the offset into the trap vector table.

Bits 3:0 are zero. This means that the TBR will always represent hexadecimal memory addresses that end in 0 (addresses that are on 4-word boundaries).

WIM ” Window Invalid Mask

The 32-bit WIM register contains a bit for each possible window in the SPARC Version 8 implementation. The low-order bit represents window 0. The high-order bit represents window 31. One bit is normally set and marks the point at which a window overflow or underflow would occur. This could result in destruction of the register contents if not correctly handled, so a trap is issued if an instruction would result in making this window available for use.

The WIM register is used in conjunction with the CWP (Current Window Pointer) during window shifts. We will be discussing this use in more detail later on.

Y ” Multiply/Divide Register

32-bit by 32-bit multiplication can result in up to 64-bit results. The most significant 32 bits are stored in the Y register. The Y register is also used during division and holds the most significant word of the dividend.

The Version 7 architecture, which had no full multiply or divide, used this register as temporary storage for individual "steps" in a multiplication or division sequence.

ASRs ” Ancillary Status Registers (optional)

The SPARC Version 8 Specification allows for up to 31 additional registers. Ancillary registers 1 through 15 are reserved for future use. ASRs 16 through 31 can be used as desired by each implementation.

The Solaris operating systems assume that no ASRs are available for use.

DTQs - Deferred-Trap Queues (optional)

According to the SPARC Version 8 Specification, an implementation may contain zero or more deferred-trap queues on the processor. These queues would be used to implement resumable deferred-traps caused by the Integer Unit.

The Solaris operating systems assume that no DTQs are available for use.