A simplified block diagram of a PLL is shown in Figure C.1. The reference clock, REFclk, is the input clock into the ASIC. The PLL tracks the reference clock and adjusts the phase of its output, PLLout, such that REFclk and the feedback clock, FBclk, are in phase.
The phase detector compares the phase difference between the rising edge of REFclk and the rising edge of FBclk. When the two are not aligned, the phase-detector output changes to increase or decrease the voltage level on the output on the charge pump.
The charge pump and low-pass filter convert the digital output of the phase detector into an analog voltage. The low-pass filter is used to control rate of change of input voltage into the voltage-controlled oscillator (VCO).
The VCO generates the clock output. The clock frequency changes as a function of the output of the charge pump.
If the PLL is being used as a frequency multiplier , the FBclk frequency is divided before being fed into the phase detector.