Appendix C. Phase-Locked Loops (PLLs)

   

Appendix C. Phase-Locked Loops (PLLs)

Most ASICs currently developed include one or more phase-locked loop (PLL) circuits. PLLs are used for a number of reasons including reduction of on-chip clock latency, synchronization of clocks between different ASICs, frequency synthesis, and clock-frequency multiplication. ASIC vendors offer various types of PLLs based on their frequency range, pin count, size , and stability.


   
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From ASICs to SOCs. A Practical Approach
From ASICs to SOCs: A Practical Approach
ISBN: 0130338575
EAN: 2147483647
Year: 2003
Pages: 61

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