Key Features

   

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Basic OCP

• Master-slave interface with unidirectional signals

• Driven and sampled by the rising edge of the OCP clock

• Fully synchronous, no multicycle timing paths

• All signals are strictly point-to-point (except clock and reset)

• Simple request/ acknowledge protocol

  Supports data transfer on every clock cycle

  Allows master or slave to control transfer rate

• Configurable data word width

• Configurable address width

• Pipelined or blocking reads

• Specific description formats for core characteristics, interfaces (signals, timing, and configuration), performance

Simple Extensions Enhance Performance

• Burst codes link related transfers into complete transaction

• Burst transactions supported:

  Sequential (defined or undefined length)

  Streaming (FIFO)

  Core-specific (cache lines)

• Pipelined (address ahead of data) writes

• Aligned or random byte enables

• Read dataflow control

• Address space definition

Complex Extensions ”Enable Concurrency

• Thread identifiers enable:

  Interleaved burst transactions

  Out-of-order transaction completion

• Thread busy notification prevents interface blocking

• Connection identifiers enable:

  End-to-end system initiator identification

  Service priority management by system targets

Sideband Extensions ”Dedicated Signaling

• Core-specific, user -defined signals:

  System event signals (e.g., interrupts error notification)

  Synchronous reset

  Data transfer coordination (e.g., high-level flow control)

Debug and Test Interface Extensions

• Support structured full or partial scan test environments

• Scan pertains to internal scan techniques for a predesigned hard core or end user-inserted into a soft core.

• Clock Controls are used for scan testing and debug, including multiple clock domains

• IEEE 1149 supports cores with a JTAG Test Access Port

• Configurable for JTAG and Enhanced JTAG-based debug for MIPS (EJTAG), ARM, TI DSP, SPARC and others

CoreCreator

OCP-IP offers its members the use of an EDA tool created by Sonics, Inc., named CoreCreator to automate the tasks of building, simulating, verifying, and packaging OCP-compatible cores. CoreCreator also supplies a protocol checker to ensure compliance with the OCP specification. IP-core products can be fully componentized by consolidating core models, timing parameters, synthesis scripts, verification suites, and test vectors.

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