The current trend toward portable electronic devices, such as wireless multimedia systems that demand high speed for computations and complex functionality, has made the design of low-power integrated circuits more and more imperative. Since these devices run on small batteries, minimum power consumption and, therefore, increased battery life are very important for the consumers of such products. Reducing the power consumption in portable devices increases reliability as well as portability while lowering the cost of production. Therefore, the continuous need for effective methods of implementing successful low-power design techniques is a major challenge faced by ASIC/SOC designers. Traditionally, the major factors determining the design methodologies for chip designs were timing and size . Figure 5.1 shows three major independent factors influencing today's design methodologies. These factors are area, timing, and power. Here, it is assumed that other factors such as TTM and reuse have already been considered .
In Section 5.2, we define power in integrated circuits. Sources of power dissipation in CMOS devices are covered including static, short-circuit , and dynamic power dissipations.
In Section 5.3, we discuss low-power design techniques such as optimization techniques at algorithm and architectural levels. RT-level optimization techniques such as clock gating and memory-power reduction are also discussed.
In Section 5.4, we cover low-power design tools. This section should be used in conjunction with Appendix A.
Section 5.5 summarizes some tips and guidelines for designing low-power ASICs and SOCs.