2.5 Summary


Table 2.1 compared complexity, speed, cost, and available I/Os for gate arrays and standard- cell and full-custom ASICs.

The major factors involved in a design TAT are frequency of operation, number of gates, density, number of clock domains, and number of blocks and sub-blocks.

The basic front-end design flow was discussed in Section 2.2. Hierarchical methodology, the use of placement-based synthesis, and the use of ILM models are recommended for designs bigger than two million gates.

FPGA to ASIC conversion was discussed in Section 2.3. Some benefits of the conversion include:

  • Die size reduction

  • Power consumption reduction

  • Enhanced performance

  • Reliable high-volume production capacity

  • Low NRE

An overview of the verification techniques and DFT was discussed in Section 2.4. We will cover more on verification issues in Chapter 3.


From ASICs to SOCs. A Practical Approach
From ASICs to SOCs: A Practical Approach
ISBN: 0130338575
EAN: 2147483647
Year: 2003
Pages: 61

Similar book on Amazon

flylib.com © 2008-2017.
If you may any questions please contact us: flylib@qtcs.net