Table 2.1 compared complexity, speed, cost, and available I/Os for gate arrays and standard- cell and full-custom ASICs.
The major factors involved in a design TAT are frequency of operation, number of gates, density, number of clock domains, and number of blocks and sub-blocks.
The basic front-end design flow was discussed in Section 2.2. Hierarchical methodology, the use of placement-based synthesis, and the use of ILM models are recommended for designs bigger than two million gates.
FPGA to ASIC conversion was discussed in Section 2.3. Some benefits of the conversion include:
Die size reduction
Power consumption reduction
Reliable high-volume production capacity
An overview of the verification techniques and DFT was discussed in Section 2.4. We will cover more on verification issues in Chapter 3.