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Hewlett-Packard began shipping the Tachyon IC in early 1995; today it is the industrys leading Fibre Channel controller. From this evolved the Tachyon TL IC, a 64-bit PCI-to-Fibre Channel controller that focuses on arbitrated loop topologies for cost-effective , Fibre Channel mass storage designs. Both of these ICs implement the Tachyon family architecture.
Single chip Fibre Channel interface
Supports both networking and mass storage implementations
Complete hardware-based design optimized for Fibre Channel
Released to production June 1996
The Tachyon controller IC, HPFC-5000C, supports arbitrated loop, fabric, and point-to-point topologies; Class 1, 2, and 3 services; and quarter, half, and full-speed Fibre Channel data rates. The IC also provides on-chip support of FCP for SCSI initiators and targets and hardware assists for TCP/UDP/IP networking. Performance is optimized within the IC through complete concurrency with eight internal DMA channels and full duplex processing.
First released by HP to customers for development in early 1995, the Tachyon IC is currently designed in by more than 30 OEMs and has become the de facto controller IC choice for Fibre Channel.
Second generation controller IC, based on HPs Tachyon architecture
Targeted to Fibre Channel Arbitrated Loop (FC-AL) designs, including Public Loop support
Supports Class 2 and 3 services
1 Gbps Fibre Channel rate
Full duplex support with parallel inbound and outbound processing
32/64-bit PCI interface, compliant with PCI v2.1
Complete hardware handling of entire SCSI I/O via FCP on-chip assists
Full Initiator and Target mode functionality
The HPFC-5100, Tachyon TL, is a second-generation controller that leverages HPs experience in Fibre Channel, established with the original Tachyon controller. Tachyon TL focuses on mass storage applications that require FC-AL, Class 3 and 2 (ACK0), and SCSI upper layer protocol handling. Coupled with a high performance 32/64-bit PCI bus interface, Tachyon TL provides a cost-effective, high-performance mass storage solution.
Tachyon TL continues with the Tachyon architecture, a complete hardware-based state machine design. This architecture avoids on-chip microprocessor performance issues of a single processing resource, processor cycles per second, and access times to firmware. Rather, the Tachyon architecture is designed to realize the full potential of Fibre Channel. Tachyon TL provides the highest levels of concurrency by way of numerous independent functional blocks providing parallel processing of data, control, and commands. In addition, these blocks process at hardware speeds versus firmware speeds and automate the entire SCSI I/O in hardware. The result is minimized latency and I/O overhead, coupled with the highest levels of parallelism to provide maximum I/O rates and bandwidth.
In addition to the high performance architecture, Tachyon TL offers second-generation Fibre Channel features, such as Public Loop, Auto Status, multiple I/Os in the same loop arbitration cycle, loop map, loop broadcast, and loop directed reset. These features allow the designer to achieve higher performance in an arbitrated loop topology.
The physical layer interface is the popular 10-bit wide specification that allows interfacing to a low-cost serializer/deserializer (SerDes) IC. This is the same physical layer interface that is popular on Fibre Channel disk drives today due to its quality gigabit signaling, small form factor, and low cost.
Host bus adapters
Tachyon is a fundamental building block, compatible with Hewlett-Packards Fibre Channel solution, which includes interface controllers, physical link modules, adapters, switches, and disk drives.
The Tachyon architecture supports both networking and mass storage connections. It is a low-cost, high-performance solution with low host overhead.
Single chip Fibre Channel interface (no I/O processor required)
Supports 1062.5, 531, and 266 MBaud links
Supports three topologies: direct connect, fabric, and Fibre Channel Arbitrated Loop (FC-AL)
Supports Fibre Channel Class 1, 2, and 3 services
Supports up to 2-Kbyte frame payload for all classes of service
Sequence segmentation/reassembly in hardware
Automatic ACK frame generation and processing
On-chip support of FCP for SCSI Initiators and Targets
Supports up to 16,384 concurrent SCSI I/O transactions
Compliant with Interned MIB-II network management
Direct interface to industry standard 10- and 20-bit Gigabit Link Modules (GLM)
Hardware assists for TCP/UDP/IP networking
Parity protection on internal data path
Eight internal DMA channels
Full duplex internal architecture that allows Tachyon to process inbound and outbound data simultaneously
System Clock Frequency:
24 to 40 MHz backplane operation
0 to 50 degrees C @ 0 m/s airflow
0 to 70 degrees C @ 1.5 m/s airflow
Full internal scan path
IEEE standard 1149.1 Boundary Scan
208-pin metal quad flat pack
Intended to be compliant with ANSI standards and FCSI/FCA profile definitions
(Hewlett-Packard reserves the right to alter specifications, features, capabilities, functions, and even general availability of the product at any time.)
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