10.2 Frequency-Hopping Spread Spectrum

In this section, features of the FHSS wireless Ethernet are highlighted by examining the packet structure, the Gaussian frequency shift keying modulation process, and basics of the frequency-hopping mechanism.

10.2.1 Summary of FHSS Standards

The packet format for the FHSS implementation of wireless Ethernet is shown in Figure 10.12. An FHSS packet consists of a preamble, a header, and a whitened MAC frame. The FHSS preamble has a Sync field of 80 bits and a Start Frame Delimiter of 16 bits. The FHSS header has a PSDU length word (PLW) of 12 bits, a Physical Layer Convergence Protocol (PLCP) signaling field (PSF) of 4 bits, and a header error check (HEC) field of 16 bits, where PLCP stands for physical layer convergence protocol and PSDU stands for PLCP SDU (Service Data Unit). PLCP is a physical layer-dependent function connecting the MAC to a particular transmission mechanism.

Figure 10.12. FHSS Packet Format

The preamble Sync field contains an alternating zero-one pattern, starting with zero and ending with one, to be used by the receiver to detect a signal and to achieve frequency and timing synchronization with the rest of the received packet. The SFD consists of the binary pattern of 0000 1100 1011 1101 used for start of frame indication. The PLW specifies the number of bytes contained in the PSDU and is used by the receiver to determine the last bit in the packet. The PSF is used to indicate the transmission throughput. These values are 0000 and 0010 for 1 and 2 Mbps, respectively. The HEC uses the CCITT CRC-16 generator polynomial G(x) = x¹⁶ + x¹² + x⁵ + 1. The HEC is the one's complement of the exclusive OR of the remainder of x³¹ + x³⁰+ … + x¹⁷ + x¹⁶ divided by G(x) and the remainder of the PSF and PLW fields multiplied by x¹⁶ and divided also by G(x).

As a typical implementation, at the transmitter, the initial remainder of the division is preset to all ones and is then modified by division of the PSF and PLW fields by the generator polynomial, G(x). The one's complement of this remainder is inserted in the HEC field with the most significant bit transmitted first. At the receiver, the initial remainder of the division is again preset to all ones. The division of the received PSF, PLW, and HEC fields by the generator polynomial, G(x), results, in the absence of transmission errors, in a unique nonzero value, representable by the polynomial R(x) = x¹² + x¹¹ + x¹⁰ + x⁸ + x³ + x² + x + 1. The MAC frame is whitened, or scrambled, using a pseudo-random sequence of length 127. This pseudo-random sequence is created based on the generator polynomial S(x)=x⁷ + x⁴ + 1. The original MAC frame is exclusive ORed with the repetition of this pseudo-random sequence to form the whitened MAC frame. In addition, a synchronization symbol is inserted after the header and after every 32 of whitened MAC frame symbols.

The synchronization symbol is initialized to 0 for 1 Mbps and to 00 for 2 Mbps. Meanwhile, an accumulation of bias is established by summarizing weights of each symbol starting with these header bits. For 1-Mbps two-level Gaussian frequency shift keying (2GFSK) modulation, a 1 has a weight of 2 and a 0 has a weight of 2. For 2-Mbps four-level Gaussian frequency shift keying (4GFSK) modulation, weights are 3, 1, 1, and 3 for 10, 11, 01, and 00 bit combinations, respectively. Whenever the bias accumulation of a 32-symbol block is different than the previous total bias accumulation, the leading synchronization symbol and following 32 symbols of the block are all negated for subsequent transmission and inclusion to the total bias accumulation. The negation of 2-Mbps symbols is equivalent to reversing the most significant bit of these bit combinations. These negated symbols can be recovered at the receiver by recognizing a 1-bit or a 10-bit combination as the leading synchronization symbol.

For 1-Mbps 2GFSK modulation, a symbol for a 1 bit is represented by a positive frequency shift of 160 kHz from the carrier frequency, and a symbol for a 0 bit is represented by a negative frequency shift of 160 kHz from the same carrier frequency. For 2-Mbps 4GFSK modulation, there are four possible frequency shifts of ±72 kHz and ±216 kHz. Bit combinations of 10, 11, 01, and 00 are represented by frequency shifts of 216, 72, 72, 216 kHz, respectively. There are 79 carrier frequencies defined for FHSS in North America and most of Europe, with applications starting at 2.402 GHz and ending at 2.48 GHz. Adjacent carrier frequencies are 1 MHz apart. The GFSK is realized by sending a voltage proportional to the desired frequency shift through a Gaussian filter to a Voltage-Controlled Oscillator. A Gaussian filter is unique in that its frequency and time domain impulse responses have the same Gaussian distribution shape.

The normalized Gaussian filter frequency response can be described by

Equation 10.3

The 3 dB bandwidth of this Gaussian filter can be derived by letting and solving for . The corresponding time domain impulse response can be obtained by using a Fourier transform of the frequency response represented by

Equation 10.4

FHSS standards recommend the use of a f_3dBT = 0.5 Gaussian modulation. For a symbol rate of 1 MHz, T = 1 x 10 ⁶, f_3dB = 0.5 x 10⁶ Hz, and a = 1.1774 x 10 ⁶. We have , , and .

The time impulse response disappears quickly beyond the baud interval. An FHSS transceiver needs to generate RF signals that are at least 10 dBm but not to exceed 20 dBm. Averaged over a bandwidth of 1.32 MHz for 1 Mbps or 1.432 MHz for 2 Mbps, the maximum PSD levels are 41.2 and 41.6 dBm/Hz, respectively.

Within the 2.4-GHz ISM band, 79 frequency channels that are 1 MHz apart are located for FHSS transceivers starting with channel 0 at 2.402 GHz and ending with channel 79 at 2.48 GHz. Among these channels, 78 of them are used for three hopping frequency sets. They are set 1 with channels of 0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39,42, 45, 48, 51, 54, 57, 60, 63, 66, 69, 72, and 75; set 2 with channels of 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 43, 46, 49, 52, 55, 58, 61, 64, 67, 70, 73, and 76; and set 3 with channels of 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59, 62, 65, 68, 72, 74, and 77. Within each set, channel frequencies are 3 MHz apart. Using different hopping frequency sets, up to three different FHSS wireless networks can be created within the same area.

A hopping sequence can be established for a particular FHSS wireless network by defining a random sequence of channel numbers using all available channels or selected channels from a specific set. The minimum frequency hop is 6 MHz. This random channel hopping sequence is repeated over and over again for continuous operations. Multiple communication links can also be established simultaneously by choosing a different starting channel. They do not interfere with each other as long as they are hopping at the same rate. The minimum hopping rate is 2.5 hops per second. A specific hopping sequence and hopping rate can be defined at the initiation of an FHSS wireless network at the access point. This information can be made available through beacon or probe frames when other transceivers join the same wireless network. A reference hopping sequence using all available channels is listed in the standards. The carrier frequency switch needs to be completed in a time frame of 224 µs. In comparison, the longest FHSS packet could last about 19 ms, and the longest hopping duration could be 400 ms. A hopping rate of 50 hops per second can accommodate at least one packet per hop.

10.2.2 Transceiver Architecture and Performance Estimation

Figure 10.13 shows a functional block diagram of a typical FHSS wireless Ethernet transceiver. In the transmit path, a phase locked loop is used to generate stable hopping carriers at half of these channel frequencies. The half frequency is chosen to avoid injection locking where the strong output from the power amplifier might interfere with the operation of the VCO. The PLL frequency is specified digitally via a register connected to the system microcontroller. The PLL is used only at the beginning of a transmit operation. After it is set to the correct hop frequency, the PLL is open and the VCO is controlled by the data sequence during the transmission of a packet. The voltage obtained by PLL for the hop frequency is increased or decreased slightly via a Gaussian filter to produce desired frequency shifts.

Figure 10.13. FHSS Transceiver Structure

A power amplifier is used to boost the doubled frequency carrier to the proper power level. The antenna is switched either to the power amplifier for transmission or to the RF amplifier for reception. Because of this half-duplex operation, the same carrier is also used to convert the RF signal to an IF signal for further amplification in the receiving path. The amplified IF signal is amplitude-limited for FSK demodulation and data sequence recovery. Filters are used between different functional stages to eliminate out-of-band noises.

After the PLL is attached to a wireless network coordinated by beacons from an access point, it regularly changes VCO's frequency to be in synchronization with the hop sequence and its timing. To transmit a packet, a clear channel is determined first by examining if the output level of the received signal strength indication (RSSI) functional block is below a certain threshold. During the normal receiving mode, the arrival of a packet is indicated when the output of RSSI exceeds another threshold. The threshold for packet detection can be higher than that of clear channel assessment to guarantee a successful packet recovery. The destination address of the arrived packet is usually checked first to determine if the rest of the packet needs to be recovered.

Figure 10.14 shows an example of an FHSS radio transceiver chip, LMX3162, from National Semiconductor. The LMX3162 contains PLL, transmit, and receive functions. The 1.3-GHz PLL is shared by transmit and receive sections. The transmitter includes a frequency doubler and a high-frequency buffer. The receiver consists of a 2.5-GHz low-noise mixer, an IF amplifier, a high-gain limiting amplifier, a frequency discriminator, an RSSI, and an analog DC compensation loop. The PLL, doubler, and buffers can be used to implement open-loop modulation along with an external VCO and loop filter. The circuit features on-chip voltage regulation to allow supply voltages ranging from 3.0 to 5.5 V. Two additional voltage regulators provide a stable supply source to external discrete stages in the Tx and Rx chains. The IF amplifier, high-gain limiting amplifier, and discriminator are optimized for 110-MHz operation, with a total IF gain of 85 dB. The RSSI output may be used for channel quality monitoring.

Figure 10.14. A Radio Transceiver Realization Example

Figure 10.15 shows the application of this radio transceiver chip for a complete FHSS transceiver. Additional components include a receive LNA, a power amplifier, an RF bandpass filter connected to the antenna, an RF bandpass filter after the LNA, a surface acoustic wave (SAW) IF bandpass filter, an inductor capacitor (LC) IF bandpass filter, a VCO, a loop filter for PLL, an RLC tank circuit for FSK demodulation, an RC low-pass filter in conjunction with FSK demodulation, and a microcontroller with a operating system and MAC software. The whole transceiver is usually assembled as a module of compact size. The use of a module for further system integration avoids potential complications when RF and IF parts are placed improperly causing performance degradation.

Figure 10.15. Application of the Example Chip

The transmit power of an FHSS transceiver is defined to be between 10 and 20 dBm. An FHSS transceiver needs to operate under the received signal level of 20 dBm when transceivers are only about 3 ft apart. The receive sensitivity is also required to be 80 dBm for the 2GFSK modulation. The allowed signal attenuation is between 90 and 100 dB. The attenuation is about 65 dB when transceivers are 50 ft apart according to Figure 5.10 at 2.4 GHz. The distance between transceivers is about 800 ft apart for an attenuation of 90 dB using the 6-dB loss per double distance rule of Equation 5.29. On the other hand, the receiver front-end noise level, P_noise, can be calculated according to the input resistor thermal noise level P_R=kT=-174 dBm/Hz, the antenna and amplifier noise figure NF=14dB, and the signal bandwidth B = 1 x 10⁶. We have

Equation 10.5

At a signal-to-noise level of about 30 dB, the channel capacity for the FHSS environment is

Equation 10.6

The transmission performance of an FHSS wireless Ethernet transceiver can be further studied by computer simulation. Figure 10.16 shows a simplified Simulink model consisting of a random data sequence generator, a Gaussian filter, a VCO, and a Frequency Shift Keying (FSK) demodulation part. The data sequence generator consists of a binary sequence generator in conjunction with a scaling circuit consisting of a fixed gain of 2, a subtractor, and a constant of 1 to convert binary to ±1 levels. The Gaussian filter operates at five times the symbol rate, and an interpolation device is used to increase the sampling rate from the data sequence generator. The VCO has a carrier frequency of 10 MHz (to simplify simulation) and a sensitivity of 160 kilohertz per volt (kHz/volt). A fourth-order Butterworth low-pass filter with a corner frequency of 750 kHz and a sampling rate of 100 MHz is used in the Frequency Modulation (FM) demodulator.

Figure 10.16. A Simulink FHSS Transceiver Model