Table 2-1: SIMD instruction set with data width in bits and bytes
Chapter 3: Processor Differential Insight
Table 3-1: 80x86 data types
Table 3-2: SIMD instruction with register names and bit widths
Table 3-3: 64-bit mode registers
Table 3-4: 32-bit (Protected/Real Mode) registers
Table 3-5: 64-, 32-, and 16-bit general-purpose registers
Table 3-6: Mappings of inc/dec instructions that use the opcode 40h-4Fh in compatibility or legacy 32-bit mode.
Table 3-7: Mappings of opcode 40h-4Fh in 64-bit mode
Table 3-8: Mappings of mod r/m code. 32-bit is the default. Substitute 16/64-bit for 32-bit form where needed, such as 00-001 DS:[ECX], DS:[CX], [RCX].
Table 3-9: RFLAG/EFLAG(s) and bit encoding
Table 3-13: String function and associated index register(s)
Chapter 4: Bit Mangling
Table 4-1: A half- adder solution. By ignoring the carry, a logical XOR will result.
Chapter 5: Bit Wrangling
Table 5-1: An 8-bit mask for stripping bits in conjunction with shifting data (07) bits to the left or to the right
Table 5-2: Instruction substitution table to convert a previous SLL (Shift Left Logical) instruction into a SRL (Shift Right Logical), as well as masks and their complement
Chapter 6: Data Conversion
Table 6-1: Correlation between little- and big-endian orientation and whether a byte swap or a stub function is implemented
Chapter 8: Floating-Point Anyone?
Table 8-1: Single-precision floating-point number representations. Sign bit. x e Exponent. Note: The integer bit of (1) 1.### is implied for single-precision and double-precision numbers .
Table 8-2: Single-precision floating-point to hex equivalent
Table 8-3: Double-precision floating-point to hex equivalent
Table 8-4: Double extended-precision floating-point to hex equivalent
Table 8-5: (16-bit) FPU status register
Table 8-6: (16-bit) FPU control word
Table 8-7: FPU exceptions
Table 8-8: FPU constants
Table 8-9: Note the single-precision loss between the 0.001 displacement as the number of digits goes up in the base number. As the base number gets larger, fewer decimal places of precision can be supported. The hexadecimal numbers in bold are where the precision was totally lost.
Table 8-10: This is a similar single-precision table except the displacement is between 0.0000001. Note the larger number of hexadecimal numbers in bold indicating a loss of precision.
Table 8-11: Note that accuracy of the precision of the numbers diminishes as the number of digits increases .
Chapter 9: Comparison
Table 9-1: SSE SPFP and DPFP immediate compare codes
Chapter 10: Branching
Table 10-1: Comparison types. The same value types are contained with an individual cell . Complement types (opposites) are across from each other.
Table 10-2: Device, interrupt, address, and IRQ mappings for PC
Chapter 15: Binary-Coded Decimal (BCD)
Table 15-1: ASCII numerical digit to hex and decimal values
Chapter 18: System
Table 18-1: Control register 0 (CR0) extensions
Table 18-2: Control register 3 (CR3) extensions
Table 18-3: Control register 4 (CR4) extensions
Table 18-4: Control register 8 (CR8) extensions. This is new for EM64T.