| 1: | Why do hardware makers extend an already successful architecture? |
| 2: | What are the drawbacks of extending an architecture, and what are some of the ways in which compatibility can be assured? |
| 3: | What are the competing demands for transistors on a chip that must be kept in some balance in new implementations of an architecture? |
| 4: | Cite one or two machine instructions, absent from Itanium architecture but present in other architectures, that you would advocate as additions in any extension of the architecture. Discuss both the difficulties and the opportunities. |
| 5: | Unlike its predecessor, the Itanium 2 processor initiates seek operations for data from the L1 and L2 caches at the same time. Derive an access-time equation for a two-level cache with simultaneous seeks from the two levels and then a sequential seek from main memory on a cache miss. This will differ from the situation described in exercise 14 in Chapter 4, where sequential seek operations were implied. |
| 6: | Explain how it is possible for an Itanium 2 processor to execute the equivalent of one three-source floating-point operation on every register rotation in a software-pipelined loop (i.e. obtaining three sources, conducting an operation, and storing a result for different pipeline stages). Then explain why it is not possible for an original Itanium processor to attain that level of throughput. |
| 7: | Revisit exercise 3 in Chapter 10. What pairs of Itanium bundle templates can execute simultaneously on an Itanium 2 processor implementation that could not execute simultaneously on the initial Itanium processor. Cite some of the reasons for the difference. |
| 8: | The tag13 operand for the brp instruction is actually encoded as a 9-bit signed immediate displacement between the bundle containing the branch and the bundle containing this instruction: (timm9 = tag13 IP)/16. How close does the brp instruction have to be to the branch instruction for which it offers a prediction? |
| 9: | (Manual search) If some later implementation of the Itanium architecture were to have a 64-bit integer multiply instruction to be carried out in general registers instead of floating-point registers, what would you propose for its assembler syntax? Explain whether you would make this new operation a type A or type I instruction, and why. What major opcode and subcodes would you assign to it? |
| 10: | (Project) Revisit the named programs and major code fragments from this book in order to spot aspects of them that you feel would run better on a system with an Itanium 2 processor than a system based on the first Itanium processor of similar nominal clock speed. Indicate for each case whether the improvement is (a) unconditional, (b) dependent upon recompiling, or (c) attainable only by rewriting the source code. |
| 11: | (Project) Research another computer architecture, either past or present, and report on the expansion of its instruction set over time, the rationale for modifications, and the ways in which the potential adverse impact of those changes upon compatibility for extant or new software was mitigated. |
