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6.5 Self-Timed and Speed-Independent Circuits

Although synchronous system design is our preferred approach, it is not always possible to build a complete system this way. As digital systems become larger, incorporating more components, or faster, running at higher clock rates, the limiting problem becomes how to distribute a single global clock without introducing intolerable clock skew.

6.5.1 Locally Clocked, Globally Delay-Insensitive Approach

When a global clocking approach is inappropriate, the alternative is to partition the digital system into locally clocked pieces that communicate with each other using delay-insensitive signaling conventions.

A delay-insensitive protocol allows the sender and receiver to communicate with each other without the need for a global clock. Each proceeds at its own speed, synchronizing its communications when it needs to interact.

A good example of this locally clocked, globally delay-insensitive approach can be found in just about every digital system constructed from multiple printed circuit boards. Each board contains its own independent clock, and the logic on the board is designed to be fully synchronous. When one board needs to communicate with another, special signaling conventions are used that have been designed to be insensitive to delay. We examine these conventions next.

6.5.2 Delay-Insensitive Signaling

The concept of delay-insensitive signaling is shown graphically in Figure 6.49 and Figure 6.50.

One subsystem is called the requester, client, or master, while the other is called the provider, server, or slave. It is common for a given component to contain logic that allows it to be either a master or a slave. For data to flow from the master to the slave, the master must make an explicit request to the slave. If the master requests a read, the slave responds by providing the requested data and signals an acknowledgment when the data is ready for the master.

Synchronous Delay-Insensitive Signaling There is no reason why the communication between the requester and the provider cannot proceed in a completely synchronous manner. This is demonstrated by the timing diagram of Figure 6.51.

The protocol is synchronous because the request and acknowledgment signals are asserted with the rising edge of the clock. They can be sampled on the falling edge.

If it is known that the slave will respond in a certain number of cycles, an acknowledgment signal is not strictly needed. However, this method can be inefficient if there is a wide variation among the speeds of potential slaves. We would have to set the number of cycles to that of the slowest slave.

To provide at least some degree of speed independence, an alternative signaling convention allows the slave to delay the master by asserting a wait signal if it cannot satisfy the request in the allotted number of cycles. This is shown in Figure 6.52.

When the slave unasserts this signal, it implicitly acknowledges that the data is available for the master. This signaling still assumes a single global clock and that all interface signals change synchronously with clock edges.

Delay Insensitivity Without a Clock: Four-Cycle Handshaking True speed-independent signaling can no longer assume that signals change with respect to a global clock. A component that asserts a signal must ensure that the signal has been observed by the component for which it is intended. This requires that the signals be interlocked: a request cannot be unasserted until the target acknowledges that it has been seen and acted on.

A four-cycle interlocked handshake, sometimes called return-to-zero signaling, is shown in Figure 6.53.

Initially, both request and acknowledge are at 0. The request for data is initiated by asserting the request signal. Because the clocks of the master and slave are unrelated, the master can make no assumptions about how long it takes for the slave to notice the request. That the request has been seen and acted on is indicated only by the slave's assertion of its acknowledgment signal. This is driven high only after the requested data has been placed on the data signal lines.

Similarly, the slave cannot make assumptions about whether the master has seen its acknowledgment signal. It must wait, continuing to drive the data and the acknowledgment until the master communicates that the data has been latched by unasserting its request signal. Now the slave can stop driving the data and can reset its acknowledgment to 0. The acknowledgment signal must become unasserted before a new request can be made.

Four-cycle signaling guarantees that the master and slave will behave properly in all timing scenarios. The request signal is asynchronous to the slave and the acknowledgment is asynchronous to the master: both must be synchronized and provide the unavoidable potential for synchronizer failure.

Two-Cycle Handshaking An alternative to four-cycle signaling is called two-cycle or non-return-to-zero signaling. The waveforms are shown in Figure 6.54.

Initially, both request and acknowledge are at 0. The master makes a request by complementing the request line, in this case driving it high. Eventually, the slave notices the change in request state, services the request, and acknowledges that the data is available by complementing its acknowledgment line, driving it high.

The master makes its next request by complementing the request line once again, driving it low. The slave stops driving the data lines with their old data, services the new request, places new data on the data lines, and signals that it has accomplished its task by complementing the acknowledge line, driving it low.

Although two-cycle signaling involves fewer transitions to accomplish the same function as four-cycle signaling, it requires that the master and slave contain an additional state to recognize a change in the request/acknowledge signal lines. Four-cycle signaling usually requires less hardware for its implementation.

Self-Timed Circuits Using the request/acknowledgment signaling conventions just described, we can build internally clocked circuit components that communicate with each other in a speed-independent manner. It is also possible to build these components so that they do not contain any internal clocks.

These unclocked circuits are sometimes called self-timed circuits. A self-timed circuit can determine on its own when a given request has been serviced. This usually involves mimicking the worst-case propagation delay path by using special logic to delay the request signal.

This scheme for a self-timed combinational logic block is shown in Figure 6.55.

The delay line merely slows down the acknowledgment signal, derived from the request signal, long enough to guarantee that the combinational logic has sufficient time to compute the correct output. If the worst-case delay path is n gate levels deep, the delay line should be a comparable number of gate levels.

Self-timed systems continue to interest designers as integrated circuits become denser and the problems of clock distribution become even more significant. Many complex VLSI circuits, such as dynamic memory chips, contain self-timed elements, and a whole microprocessor has been constructed in a self-timed manner. More information about self-timed circuits and systems can be found in the references at the end of this chapter.

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This file last updated on 07/14/96 at 15:33:06.
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