RAM Types and Performance
| The speed and performance issue with memory is confusing to some because memory speed is usually expressed in ns (nanoseconds) and processor speed has always been expressed in MHz (megahertz). Recently, however, some newer and faster types of memory have speeds expressed in MHz, adding to the confusion. Fortunately, you can translate one to the other. A nanosecond is defined as one billionth of a seconda very short time indeed. To put some perspective on that, the speed of light is 186,282 miles (299,792 kilometers) per second in a vacuum. In one billionth of a second, a beam of light travels a mere 11.80 inches or 29.98 centimetersless than the length of a typical ruler! Chip and system speed has been expressed in megahertz (MHz), which is millions of cycles per second, or gigahertz (GHz), which is billions of cycles per second. During 2005, systems will exceed 5GHz or 5 billion cycles per second. Today's processors continue to run in the 2GHz4GHz range with most performance improvements coming from changes in CPU design rather than pure clock speed. Because it is confusing to speak in these different terms for speeds, I thought it would be interesting to see how they compare. Earlier in this chapter I listed formulas you could use to mathematically convert these values. Table 6.3 shows the relationship between common nanosecond (ns) and megahertz (MHz) speeds associated with PCs from yesterday to today and tomorrow.
As you can see from Table 6.3, as clock speeds increase, cycle time decreases proportionately. If you examine Table 6.3, you can clearly see that the 60ns DRAM memory used in the original Pentium and Pentium II PCs up until 1998 works out to be 16.7MHz! This super-slow 16.7MHz memory had been installed in systems running up to 300MHz or faster, and you can see that a large mismatch existed between processor and main memory performance. The dominant standard in 2000 was to have 100MHz and even 133MHz memory, called PC100 and PC133, respectively. Starting in early 2001, double data rate (DDR) memory of 200MHz and 266MHz become popular, along with 800MHz RDRAM. In 2002 standard 333MHz DDR memory arrived, and in 2003, the speeds increased to 400MHz. During 2004, we saw the introduction of DDR2 first at 400MHz and then at 533MHz. At the end of 2005, DDR memory was available at speeds up to 533MHz and DDR2 memory was available at speeds up to 1000MHz. System memory timing is a little more involved than simply converting nanoseconds to megahertz. The transistors for each bit in a memory chip are most efficiently arranged in a grid, using a row and column scheme to access each transistor. All memory accesses involve selecting a row address and then a column address and then transferring the data. The initial setup for a memory transfer where the row and column addresses are selected is a necessary overhead referred to as latency. The access time for memory is the cycle time plus latency for selecting the row and column addresses. For example, SDRAM memory rated at 133MHz (7.5ns) typically takes five cycles to set up and complete the first transfer (5x7.5ns = 37.5ns) and then perform three additional transfers with no additional setup. Thus, four transfers take a total of eight cycles, or an average of about two cycles per transfer. Over the development life of the PC, memory has had a difficult time keeping up with the processor, requiring several levels of high-speed cache memory to intercept processor requests for the slower main memory. Table 6.4 shows the progress and relationship between system board (motherboard) speeds in PCs and the various types and speeds of main memory or RAM used and how these changes have affected total bandwidth.
Generally, things work best when the throughput of the memory bus matches the throughput of the processor bus. Compare the memory bus transfer speeds (bandwidth) to the speeds of the processor bus as shown in Table 6.5, and you'll see that some of the memory bus rates match that of some of the processor bus rates. In most cases the type of memory that matches the CPU bus transfer rate is the best type of memory for systems with that type of processor.
Because the processor is fairly well insulated from directly dealing with main memory by the L1 and L2 cache, memory performance has often lagged behind the performance of the processor bus. More recently, however, systems using SDRAM, DDR SDRAM, and RDRAM have memory bus performance equaling that of the processor bus. When the speed of the memory bus equals the speed of the processor bus, memory performance is optimum for that system. Fast Page Mode DRAMStandard DRAM is accessed through a technique called paging. Normal memory access requires that a row and column address be selected, which takes time. Paging enables faster access to all the data within a given row of memory by keeping the row address the same and changing only the column. Memory that uses this technique is called Page Mode or Fast Page Mode memory. Other variations on Page Mode were called Static Column or Nibble Mode memory. Paged memory is a simple scheme for improving memory performance that divides memory into pages ranging from 512 bytes to a few kilobytes long. The paging circuitry then enables memory locations in a page to be accessed with fewer wait states. If the desired memory location is outside the current page, one or more wait states are added while the system selects the new page. To improve further on memory access speeds, systems have evolved to enable faster access to DRAM. One important change was the implementation of burst mode access in the 486 and later processors. Burst mode cycling takes advantage of the consecutive nature of most memory accesses. After setting up the row and column addresses for a given access, using burst mode, you can then access the next three adjacent addresses with no additional latency or wait states. A burst access usually is limited to four total accesses. To describe this, we often refer to the timing in the number of cycles for each access. A typical burst mode access of standard DRAM is expressed as x-y-y-y; x is the time for the first access (latency plus cycle time), and y represents the number of cycles required for each consecutive access. Standard 60ns DRAM normally runs 5-3-3-3 burst mode timing. This means the first access takes a total of five cycles (on a 66MHz system bus, this is about 75ns total or 5x15ns cycles), and the consecutive cycles take three cycles each (3x15ns = 45ns). As you can see, the actual system timing is somewhat less than the memory is technically rated for. Without the bursting technique, memory access would be 5-5-5-5 because the full latency is necessary for each memory transfer. DRAM memory that supports paging and this bursting technique is called Fast Page Mode (FPM) memory. The term comes from the capability of memory accesses to data on the same page to be done with less latency. Most 486 and Pentium systems from 1995 and earlier use FPM memory. Another technique for speeding up FPM memory was called interleaving. In this design, two separate banks of memory are used together, alternating access from one to the other as even and odd bytes. While one is being accessed, the other is being precharged, when the row and column addresses are being selected. Then, by the time the first bank in the pair is finished returning data, the second bank in the pair is finished with the latency part of the cycle and is now ready to return data. While the second bank is returning data, the first bank is being precharged, selecting the row and column address of the next access. This overlapping of accesses in two banks reduces the effect of the latency or precharge cycles and allows for faster overall data retrieval. The only problem is that to use interleaving, you must install identical pairs of banks together, doubling the amount of SIMMs or DIMMs required. This method was popular on 32-bit wide memory systems on 486 processors but fell out of favor on Pentiums because of their 64-bit wide memory widths. To perform interleaving on a Pentium machine, you would need to install memory 128 bits at a time, meaning four 72-pin SIMMs or two DIMMs at a time. Extended Data Out RAMIn 1995, a newer type of memory called extended data out (EDO) RAM became available for Pentium systems. EDO, a modified form of FPM memory, is sometimes referred to as Hyper Page mode. EDO was invented and patented by Micron Technology, although Micron licensed production to many other memory manufacturers. EDO memory consists of specially manufactured chips that allow a timing overlap between successive accesses. The name extended data out refers specifically to the fact that unlike FPM, the data output drivers on the chip are not turned off when the memory controller removes the column address to begin the next cycle. This enables the next cycle to overlap the previous one, saving approximately 10ns per cycle. The effect of EDO is that cycle times are improved by enabling the memory controller to begin a new column address instruction while it is reading data at the current address. This is almost identical to what was achieved in older systems by interleaving banks of memory, but unlike interleaving, with EDO you didn't need to install two identical banks of memory in the system at a time. EDO RAM allows for burst mode cycling of 5-2-2-2, compared to the 5-3-3-3 of standard fast page mode memory. To do four memory transfers, then, EDO would require 11 total system cycles, compared to 14 total cycles for FPM. This is a 22% improvement in overall cycling time, but in actual testing, EDO typically increases overall system benchmark speed by about 5%. Even though the overall system improvement might seem small, the important thing about EDO was that it used the same basic DRAM chip design as FPM, meaning that there was practically no additional cost over FPM. In fact, in its heyday, EDO cost less than FPM and yet offered higher performance. EDO RAM generally comes in 72-pin SIMM form. Figure 6.4 (later in this chapter) shows the physical characteristics of these SIMMs. Figure 6.2. SDR (single data rate) versus DDR (double data rate) cycling. Figure 6.3. A typical 30-pin SIMM. Figure 6.4. A typical 72-pin SIMM. To actually use EDO memory, your motherboard chipset must support it. Most motherboard chipsets on the market from 1995 (Intel 430FX) through 1997 (Intel 430TX) offered support for EDO. Because EDO memory chips cost the same to manufacture as standard chips, combined with Intel's support of EDO in all its chipsets, the PC market jumped on the EDO bandwagon full force.
EDO RAM was ideal for systems with bus speeds of up to 66MHz, which fit perfectly with the PC market up through 1997. However, since 1998 with the advent of faster system bus speeds (100MHz and above), the market for EDO has rapidly declined as the newer and faster SDRAM architecture has become the standard for new PC system memory. A variation of EDO is burst EDO (BEDO). BEDO is basically EDO memory with special burst features for even speedier data transfers than standard EDO. Unfortunately, the technology was owned by Micron and not a free industry standard, so only one chipset (Intel 440FX Natoma) ever supported it. BEDO was therefore quickly overshadowed by industry-standard SDRAM, which was favored among PC system chipset and system designers over proprietary designs. As such, BEDO never really saw the light of production, and to my knowledge no systems ever really used it. SDRAMSDRAM is short for synchronous DRAM, a type of DRAM that runs in synchronization with the memory bus. SDRAM delivers information in very high-speed bursts using a high-speed, clocked interface. SDRAM removes most of the latency involved in asynchronous DRAM because the signals are already in synchronization with the motherboard clock. Like EDO RAM, your chipset must support this type of memory for it to be usable in your system. Starting in 1996 with the 430VX and 430TX, most of Intel's chipsets began to support industry-standard SDRAM, making it the most popular type of memory for new systems into 2001. SDRAM performance is dramatically improved over that of FPM or EDO RAM. Because SDRAM is still a type of DRAM, the initial latency is the same, but overall cycle times are much faster than with FPM or EDO. SDRAM timing for a burst access would be 5-1-1-1, meaning that four memory reads would complete in only eight system bus cycles, compared to eleven cycles for EDO and fourteen cycles for FPM. This makes SDRAM almost 20% faster than EDO. Besides being capable of working in fewer cycles, SDRAM is also capable of supporting up to 133MHz (7.5ns) system bus cycling. As such, most new PC systems sold from 1998 to 2000 have included SDRAM memory. SDRAM is sold in DIMM form and is often rated by megahertz speed rather than nanosecond cycling time, which was confusing during the change from FPM and EDO DRAM. Figure 6.5 (later in this chapter) shows the physical characteristics of DIMMs. Figure 6.5. A typical 168-pin SDRAM DIMM. To meet the stringent timing demands of its chipsets, Intel created specifications for SDRAM called PC66, PC100, and PC133. To meet the PC100 specification, 8ns chips usually are required. Normally, you would think 10ns would be considered the proper rating for 100MHz operation, but the PC100 specification calls for faster memory to ensure all timing parameters are met. In May 1999, the Joint Electron Device Engineering Council (JEDEC) created a specification called PC133. They achieved this 33MHz speed increase by taking the PC100 specification and tightening up the timing and capacitance parameters. The faster PC133 quickly caught on as the most popular version of SDRAM for any systems running a 133MHz processor bus. The original chips used in PC133 modules were rated for exactly 7.5ns or 133MHz; later ones were rated at 7.0ns or 143MHz. These faster chips were still used on PC133 modules, but they allowed for improvements in column address strobe latency (abbreviated as CAS or CL), which somewhat improves overall memory cycling time. Note JEDEC is the semiconductor engineering standardization body of the Electronic Industries Alliance (EIA), a trade association that represents all areas of the electronics industry. JEDEC was originally created in 1960 and governs the standardization of all types of semiconductor devices, integrated circuits, and modules. JEDEC has about 300 member companies, including memory, chipset, and processor manufacturers as well as practically any company involved in manufacturing computer equipment using industry-standard components. The idea behind JEDEC is simple: For example, if one company were to create a proprietary memory technology, other companies who wanted to manufacture components compliant with that memory would have to pay license fees, assuming the company that owned it was interested in licensing at all! Parts would be more proprietary in nature, causing problems with interchangeability or sourcing reasonably priced replacements. In addition, those companies licensing the technology would have no control over future changes or evolution made by the owner company. The idea behind JEDEC is to prevent this type of scenario for things such as memory by getting all the memory manufacturers to work together to create shared industry standards covering memory chips and modules. JEDEC-approved standards for memory can then be freely shared by all the member companies, and no one single company has control over a given standard, or any of the companies producing compliant components. FPM, SDRAM, DDR SDRAM, and DDR2 SDRAM are examples of JEDEC memory standards used in PCs, whereas EDO and RDRAM are proprietary examples. You can find out more about JEDEC standards for memory and other semiconductor technology at www.jedec.org. Table 6.6 shows the timing, rated chip speeds, and standard module speeds for various SDRAM DIMMs.
At one time, some module manufacturers sold modules they claim are "PC150" or "PC166" even though those speeds do not exist as official JEDEC or Intel standards and no chipsets or processors officially support these speeds. Normally, these modules actually use hand-picked 7.5ns (133MHz) or 7.0ns (143MHz) rated chips that can run overclocked at 150MHz or 166MHz speeds. In essence, PC150 or PC166 memory would more accurately be called PC133 memory that has been tested to run at overclocked speeds not supported by the original chip manufacturer. This specially selected overclockable memory was sold at a premium to enthusiasts who want to overclock their motherboard chipsets, thereby increasing the speed of the processor and memory bus. Table 6.7 shows the standard SDRAM module types and resulting bandwidths.
Caution At one time, PC133 memory was backward compatible with PC100 memory. However, currently manufactured PC133 memory uses different sizes of memory chips from those used by PC100 modules. If you need to upgrade a system that requires PC100 memory, you should not attempt to use PC133 memory in it unless the memory is specifically identified by the vendor as being compatible with your system. You can use the online memory configuration tools provided by most major memory vendors to ensure that you get the right memory for your system. DDR SDRAMDouble data rate (DDR) SDRAM memory is a JEDEC-created standard that is an evolutionary upgrade of standard SDRAM in which data is transferred twice as quickly. Instead of doubling the actual clock rate, DDR memory achieves the doubling in performance by transferring twice per transfer cycle: once at the leading (falling) edge and once at the trailing (rising) edge of the cycle (see Figure 6.2). This effectively doubles the transfer rate, even though the same overall clock and timing signals are used. DDR found initial support in the graphics card market and since then has become the mainstream PC memory standard. As such, DDR SDRAM is supported by all the major processor, chipset, and memory manufacturers. Note Although Intel has switched to DDR2 for its latest chipsets, AMD Athlon 64 and Opteron processors (which feature integrated DDR memory controllers) support only DDR as of late 2005. Thus, DDR will continue to be a mainstream memory technology through 2006. DDR SDRAM first came to market during 2000, but it didn't really catch on until 2001 with the advent of mainstream motherboards and chipsets supporting it. DDR SDRAM uses a new DIMM module design with 184 pins. Figure 6.6 (later in this chapter) shows the DDR SDRAM DIMM. Figure 6.6. A typical 184-pin DDR DIMM. DDR DIMMs come in a variety of speed or throughput ratings and normally run on 2.5 volts. They are basically an extension of the standard SDRAM DIMMs redesigned to support double clocking, where data is sent on each clock transition (twice per cycle) rather than once per cycle as with standard SDRAM. To eliminate confusion with DDR, regular SDRAM is often called single data rate (SDR). Table 6.8 compares the various types of standard DDR SDRAM modules. As you can see, the raw chips are designated by their speed in megatransfers per second, whereas the modules are designated by their approximate throughput in megabytes per second.
The bandwidths listed in these tables are per module. Many recent chipsets support dual-channel DDR memorya technique in which two DDR DIMMs are installed at one time and function as a single bank with double the bandwidth of a single module. For example, the Intel 915G, 915GV, 915GL, and 915PL chipsets use dual-channel DDR memory (some also support dual-channel DDR2 memory). They support the 800MHz Pentium 4 processor front-side bus (FSB), which transfers 8 bytes (64 bits) at a time for a bandwidth of 6,400MBps (800x8 = 6400). With an 800MHz FSB processor installed, these boards use standard PC3200 modules, installed two at a time (dual-channel), for a total bandwidth of 6,400MBps (3,200MBps x 2 = 6,400MBps). This design allows the memory bus throughput to match the CPU bus throughput exactly, resulting in the best possible performance. You can optimize PC design by ensuring that the CPU bus and memory bus both run at exactly the same speeds (meaning bandwidth, not MHz), so that data can move synchronously between the buses without delays. DDR2 SDRAMJEDEC and its members began working on the DDR2 specification in April 1998, and published the standard in September 2003. DDR2 chip and module production actually began in mid-2003 (mainly samples and prototypes), and the first chipsets, motherboards, and systems supporting DDR2 appeared in mid-2004. DDR2 SDRAM is simply a faster version of conventional DDR-SDRAM memory: It achieves higher throughput by using differential pairs of signal wires to allow faster signaling without noise and interference problems. DDR2 is still double data rate just as with DDR, but the modified signaling method enables higher speeds to be achieved with more immunity to noise and cross-talk between the signals. The additional signals required for differential pairs add to the pin countDDR2 DIMMs have 240 pins, which is more than the 184 pins of DDR. The original DDR specification tops out at 400MHz, whereas DDR2 starts at 400MHz and goes up to 1000MHz and beyond. Table 6.9 shows the various DDR2 module types and bandwidth specifications.
In addition to providing greater speeds and bandwidth, DDR2 has other advantages. It uses lower voltage than conventional DDR (1.8V versus 2.5V), so power consumption and heat generation are reduced. Because of the greater number of pins required on DDR2 chips, the chips typically use fine-pitch ball grid array (FBGA) packaging rather than the thin small outline package (TSOP) chip packaging used by most DDR and conventional SDRAM chips. FPGA chips are connected to the substrate (meaning the memory module in most cases) via tightly spaced solder balls on the base of the chip. Volume production of DDR2 chips and modules started in the latter part of 2003, with supporting chipsets and motherboards arriving in mid-2004. Variations of DDR2 such as G-DDR2 (Graphics DDR2) are being used in some of the higher-end graphics cards as well. Although all the major memory and Intel-compatible chipset makers support DDR2, the major holdout through 2005 was AMD, whose Athlon 64 and Opteron processor families include integrated DDR memory controllers. Starting in mid-2006, AMD will also support DDR2 with redesigned versions of the Athlon 64, Sempron, and Opteron processor families. DDR2 DIMMs resemble conventional DDR DIMMs but have more pins and slightly different notches to prevent confusion or improper application. For example, the different physical notches prevent you from plugging a DDR2 module in to a conventional DDR (or SDR) socket. DDR2 memory module designs incorporate 240 pins, significantly more than conventional DDR or standard SDRAM DIMMs. RDRAMRambus DRAM (RDRAM) is a fairly radical memory design found in high-end PC systems from late 1999 through 2002. Intel signed a contract with Rambus in 1996 ensuring it would support RDRAM into 2001. After 2001, Intel continued to support RDRAM in existing systems, but new chipsets and motherboards primarily shifted to DDR SDRAM, and all future Intel chipsets and motherboards are being designed for either conventional DDR or the newer DDR2 standard. RDRAM standards had been proposed that will support faster processors through 2006; however, without Intel's commitment to future chipset development and support, very few RDRAM-based systems were sold in 2003, and almost none after that. Due to the lack of industry support from chipset and motherboard manufacturers, RDRAM will most likely not play a big part in future PCs. With RDRAM, Rambus developed what is essentially a chip-to-chip memory bus, with specialized devices that communicate at very high rates of speed. What might be interesting to some is that this technology was first developed for game systems and first made popular by the Nintendo 64 game system, and it subsequently was used in the Sony Playstation 2. Conventional memory systems that use FPM/EDO or SDRAM are known as wide-channel systems. They have memory channels as wide as the processor's data bus, which for the Pentium and up is 64 bits. The dual inline memory module (DIMM) is a 64-bit wide device, meaning data can be transferred to it 64 bits (or 8 bytes) at a time. RDRAMs, on the other hand, are narrow-channel devices. They transfer data only 16 bits (2 bytes) at a time (plus 2 optional parity bits), but at much faster speeds. This is a shift away from a more parallel to a more serial design and is similar to what is happening with other evolving buses in the PC. 16-bit single channel RIMMs originally ran at 800MHz, so the overall throughput is 800x2, or 1.6GB per second for a single channelthe same as PC1600 DDR SDRAM. Pentium 4 systems typically used two banks simultaneously, creating a dual-channel design capable of 3.2GBps, which matches the bus speed of the original Pentium 4 processors. The RDRAM design features less latency between transfers because they all run synchronously in a looped system and in only one direction. Newer RIMM versions run at 1,066MHz or 1,200MHz in addition to the original 800MHz rate and are available in single-channel, 16-bit versions as well as multiple-channel, 32-bit versions for throughputs up to 4.8GBps per module. A single Rambus memory channel can support up to 32 individual RDRAM devices (the RDRAM chips), and more if buffers are used. Each individual chip is serially connected to the next on a package called a Rambus inline memory module (RIMM), but all memory transfers are done between the memory controller and a single device, not between devices. The individual RDRAM chips are contained on RIMMs, and a single channel typically has three RIMM sockets. The RDRAM memory bus is a continuous path through each device and module on the bus, with each module having input and output pins on opposite ends. Therefore, any RIMM sockets not containing a RIMM must then be filled with a continuity module to ensure that the path is completed. The signals that reach the end of the bus are terminated on the motherboard. Each RDRAM chip on a RIMM1600 essentially operates as a standalone module sitting on the 16-bit data channel. Internally, each RDRAM chip has a core that operates on a 128-bit wide bus split into eight 16-bit banks running at 100MHz. In other words, every 10ns (100MHz), each RDRAM chip can transfer 16 bytes to and from the core. This internally wide yet externally narrow high-speed interface is the key to RDRAM. Other improvements to the design include separating control and data signals on the bus. Independent control and address buses are split into two groups of pins for row and column commands, while data is transferred across the 2-byte wide data bus. The actual memory bus clock runs at 400MHz; however, data is transferred on both the falling and rising edges of the clock signal, or twice per clock pulse. The falling edge is called an even cycle, and the rising edge is called an odd cycle. Complete memory bus synchronization is achieved by sending packets of data beginning on an even cycle interval. The overall wait before a memory transfer can begin (latency) is only one cycle, or 2.5ns maximum. Figure 6.2 (shown earlier) depicts the relationship between clock and data cycles; you can see the DDR clock and data cycles used by RDRAM and DDR SDRAM. An RDRAM data packet always begins on an even (falling) transition for synchronization purposes. The architecture also supports multiple, simultaneous interleaved transactions in multiple separate time domains. Therefore, before a transfer has even completed, another can begin. Another important feature of RDRAM is that it is a low-power memory system. The RIMMs themselves as well as the RDRAM devices run on only 2.5 volts and use low-voltage signal swings from 1.0V to 1.8V, a swing of only 0.8V total. RDRAMs also have four power-down modes and can automatically transition into standby mode at the end of a transaction, which offers further power savings. As discussed, RDRAM chips are installed in modules called RIMMs. A RIMM is similar in size and physical form to current DIMMs, but they are not interchangeable. RIMMs are available in module sizes up to 1GB or more and can be added to a system one at a time because each individual RIMM technically represents multiple banks to a system. They have to be added in pairs if your motherboard implements dual-channel RDRAM and you are using 16-bit wide RIMMs. An RDRAM memory controller with a single Rambus channel supports up to three RIMM modules according to the design. However, most motherboards implement only two modules per channel to avoid problems with signal noise. RIMMs are available in three primary speed grades, with three different width versions in each grade. The 16-bit versions are usually run in a dual-channel environment, so they have to be installed in pairs, with each one of the pairs in a different set of sockets. Each set of RIMM sockets on such boards is a channel. The 32-bit version incorporates multiple channels within a single device and, as such, is designed to be installed individually, eliminating the requirement for matched pairs. Table 6.10 compares the various types of RDRAM modules. Note that the once-common names for RIMM modules, such as PC800, have been replaced by names that reflect the actual bandwidth of the module to avoid confusion with DDR memory.
When Intel initially threw its weight behind the Rambus memory, it seemed destined to be a sure thing for success. Unfortunately, technical delays in the chipsets caused the supporting motherboards to be significantly delayed, and with few systems to support the RIMMs, most memory manufacturers went back to making SDRAM or shifted to DDR SDRAM instead. This caused the remaining available RIMMs being manufactured to be originally priced three or more times that of a comparatively sized DIMM. More recently the cost for RDRAM RIMMs has come down to approximately that of DDR SDRAM, but by the time that happened, Intel had shifted all future chipset development to support only DDR and DDR2 memory. As I've stated many times, one of the main considerations for memory is that the throughput of the memory bus should match the throughput of the processor bus, and in that area RDRAM RIMMs were originally more suited to the initial Pentium 4 processor systems. However, with the increases in speed of the Pentium 4 processor bus from 400MHz to 533MHz and then 800MHz and the advent of chipsets supporting dual-channel DDR memory, DDR and DDR2 are currently the best match for the CPU bus speeds of both Intel and AMD processors. In short, the advent of newer chipsets supporting dual-channel DDR in 2002 and DDR2 in 2004 has rendered DDR and DDR2 as the best choices for modern systems, offering the maximum memory performance possible. Note Unfortunately for the memory chip manufacturers, Rambus has claimed patents that cover both standard and DDR SDRAM designs. So, regardless of whether these companies manufacture SDRAM, DDR, or RDRAM, it is the contention of Rambus that these memory manufacturers must pay the company royalties. Several court cases are ongoing with companies challenging these patents, and a lot is riding on the outcome. Most of the cases that have gone to trial have so far ruled against Rambus, essentially invalidating its patents and claims on DDR and SDRAM. Many appeals are pending, and it will likely be a long time before the patent issues are resolved. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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