Chapter10.Optimizing C for FPGA Performance

Chapter 10. Optimizing C for FPGA Performance

In Chapters 8 and 9 we presented a triple-DES encryption algorithm, showing how a process of software simulation, using standard C tools coupled with in-system testing, could be used to validate a legacy C algorithm that had been converted to an FPGA implementation. As we pointed out in those chapters, however, the performance obtained from this particular algorithm was not especially good relative to what could be achieved by a reasonably skilled VHDL or Verilog programmer.

C code that has not been written with hardware compilation in mind can result in less-than-optimal results when those results are measured in terms of process latencies, data throughput, and size of the generated logic. This is because the fundamental target of compilation (an FPGA and its constituent hardware resources) is quite different from a traditional processor, and the C language is, by design, optimized for processor-based architectures. By using some relatively simple C programming techniques, however, it is possible to dramatically accelerate the performance of many types of algorithms. This chapter presents some of these important techniques.

In Chapter 6 and 7 you learned that certain programming techniques can be applied to improve the performance of processes written in C and compiled to hardware. In this chapter we'll apply some of those techniques directly.