In this chapter we have created a mixed hardware/software application in which the software portion communicates directly with the hardware process using streams-based communications. We have shown the steps needed to generate the FPGA hardware, combine this with a soft processor and download the combined application to an actual FPGA prototyping board.
This process has allowed us to determine the correctness of the algorithm in hardware and set up an in-system test environment to directly evaluate the results of subsequent design optimizations. In effect, what we have created by doing this is a hardware/software test bench that supports unit testing of this particular algorithm. This test bench lets us validate the algorithm quickly and apply a wide variety of test inputs simply by changing and recompiling the software application, which runs on the FPGA's embedded processor.
Armed with this software/hardware test bench, we can now proceed to optimize this application for performance, secure in the knowledge that the results will be fully testable at the process level, in actual hardware.