Section 9.6. Building the Test System

9.6. Building the Test System

To run the hardware/software test using the embedded test bench just described, we need to set up a test platform using an FPGA prototyping board and configure that platform using the appropriate FPGA vendor tools. For the Xilinx MicroBlaze target, we have chosen to use the Virtex II prototyping board supplied by Insight Electronics (Memec Design). This board, which was shown in Figure 9-1, has the necessary I/O resources and other features useful for hardware/software prototyping and testing.

In this section we will go through the process, step-by-step, of creating a platform using the Xilinx Embedded Development Kit (EDK) tools. As we go through this process, keep in mind that the Xilinx and Impulse tools are in a near-constant state of change. By the time you read this description the process may be somewhat different, and quite possibly easier.

Specifying the Platform Support Package

The first step, before generating hardware, is to select a target platform in the Impulse tools. The compilation process for both hardware and software elements of the application is defined by a number of platform-specific factors, including the type of FPGA being targeted (in this case a Xilinx Virtex II device), the type of processor (the MicroBlaze), and the bus architecture to be used for data streams (FSL). Additional factors might include an embedded operating system or an unusual (board-specific) memory or I/O interface.

To specify a platform target appropriate for the V2MB1000 board we are using, we open the Generate Options dialog as shown in Figure 9-4 and choose the platform Xilinx MicroBlaze FSL. We also specify hw and sw for the hardware and software directories as shown, and specify EDK for the hardware and software export directories. Also, we ensure that the "Generate dual clocks" option is checked, which indicates that we expect to clock the FPGA component (the triple-DES encryption core) at a different clock rate than the MicroBlaze processor.

Figure 9-4. Setting the hardware generation options.

Generating HDL for the Hardware Process

To generate hardware in the form of HDL files, and to generate the associated software interfaces and library files, we select Generate HDL from the Impulse C Project menu. This invokes the compilation steps for hardware generation (see Figure 9-5). This series of operations results in the generation of

  • hw/3des_comp.vhd, which represents the encryption process

  • hw/3des_top.vhd, which represents the top-level HDL file

  • hw/core, which is a directory containing files required by the Xilinx EDK tools

  • hw/lib, which includes the Impulse library files required for FPGA synthesis and/or VHDL simulation

  • sw/co_init.c, which is linked with the software portion of your application to start up and manage the stream interfaces and other software elements

  • sw/driver, which is a directory containing runtime libraries implementing the low-level stream, signal, and memory interfaces and the various Impulse C function calls

Figure 9-5. Generating hardware for the selected target.

Creating the Platform Using the Xilinx Tools

As described earlier, the result of compilation is a number of hardware and software-related output files that must all be used to create a complete hardware/software application on the target platform. Creating that platform requires a number of additional steps, most of which are performed in the Xilinx tools.


Although this section focuses primarily on the use of the Xilinx tools and Xilinx devices, the process of creating mixed hardware/software applications for Altera-based platforms is conceptually the same. Altera provides a tool called SOPC Builder (described in Chapter 11) that provides capabilities similar to the EDK and Platform Studio tools described here. The Impulse compiler generates outputs compatible with either Xilinx or Altera platforms.

To create the platform, we need to create a new Xilinx EDK project then export the files generated by the Impulse C compiler to this new project. We will do this using the EDK System Builder (Platform Studio) tool environment.

We begin by creating a subdirectory within our project directory that will contain the new Xilinx Platform Studio (EDK) project files. For this subdirectory we have chosen the name EDK, which is also the directory name we specified earlier in the Generate Options dialog.

Creating a Platform Studio Project and Choosing a Board

Now we'll move into the Xilinx tool environment. We launch Xilinx Platform Studio and create a new project (called system.xmp, specifying that we want to use the Xilinx Base System Builder Wizard to define the platform.

The Base System Builder Wizard prompts us to choose our target board (Figure 9-6). We choose the Memec Design V2MB1000 (revision 3) board from the list. Note that board support packages such as this one are provided by the board vendors, typically on their support websites.

Figure 9-6. Selecting the target development board.

We click Next to continue with the System Builder Wizard, and in the next wizard page, we select MicroBlaze as the processor (see Figure 9-7). The other choice, PowerPC, is not available for this particular board, which does not include a PowerPC-equipped Virtex II Pro or Virtex-4 device.

Figure 9-7. Specifying the processor type.

We click Next to continue with the Base System Builder Wizard. The next steps (and corresponding series of Base System Builder screens) are summarized next. They involve configuring the MicroBlaze processor and creating the necessary I/O interfaces for the 3DES test application.

Configuring the MicroBlaze Processor

Now that we have created a basic MicroBlaze project in the System Builder Wizard, we need to specify additional information about the platform to support the requirements of the 3DES hardware/software application. Continuing with the steps required in the Base System Builder Wizard, we specify the following information in the Configure processor page, making sure to increase the local data and instruction memory, as shown in Figure 9-8.

System Wide Settings
  Reference Clock Frequency: 100 MHz
  Processor-Bus Clock Frequency: 100 MHz

Processor Configuration
  On-chip H/W debug module (default setting)
  Local Data and Instruction Memory: 64KB

Figure 9-8. Configuring the MicroBlaze processor.

We click Next to continue with the Wizard. We are now presented with a series of wizard pages specifying the I/O peripherals to be included with the MicroBlaze processor. We select one RS232 device and the SRAM_256Kx32 peripheral by setting the following options:

I/O Device: RS232
Peripheral: OPB UARTLITE
Baudrate: 9600
Data Bits: 8
Parity: NONE
Use Interrupt: disabled

I/O Device: SRAM_256Kx32
Peripheral: OPB EMC

We click Next and disable all other I/O devices, with the exception of DDR_SRAM_16Mx16 in the Additional IO Interfaces dialogs that follow.

On the Software Configuration dialog (see Figure 9-9), we select the Generate Sample Application and Linker Script option (the default) and ensure that STDIN and STDOUT are mapped to the selected RS232 interface.

Figure 9-9. Specifying the STDIN and STDOUT devices and the processor memories.

At this point we have configured the platform and processor features. The Base System Builder Wizard displays a summary of the system we have created, as illustrated in Figure 9-10. We click Generate to generate the system and project files and click Finish to close the Wizard. We exit Xilinx Platform Studio completely before beginning the next step, which is exporting our generated Impulse C hardware to the newly created platform.

Figure 9-10. Base System Builder system summary.

Exporting Files from the Impulse Tools

With Xilinx Platform Studio closed, we return to the Impulse C tools. Recall that at the start of this section we specified the directory EDK as the export target for hardware and software (in Figure 9-4). This is also the directory where we created the new Platform Studio project. These export directories specify where the generated hardware and software processes are to be copied when the Export Software and Export Hardware features of the Impulse tools are invoked. Within these target directories (in this case EDK), the specific destination subdirectory for each file previously generated is determined from the Impulse Platform Support Package architecture library files. It is therefore important that the correct Platform Support Package (in this case Xilinx MicroBlaze FSL) be selected prior to starting the export process.

To export the files from the build directories (in this case hw and sw) to the export directories (in this case the EDK directory), we select the Export Generated Hardware and Export Generated Software options from the Impulse tools. This results in the generated hardware and software files being copied into the appropriate subdirectories of our new Platform Studio project. As a result, the next time we open that project we will have available the generated Impulse C hardware in the form of a standard FSL peripheral.

Importing the Generated Hardware

We now return to the Xilinx Platform Studio application to finish creating and configuring the target platform. This next part of this procedure is somewhat lengthy but needs to be done only once for any new project. In fact, it is useful to create one template platform (using the following methods) and save that platform for later reference and use.

After navigating to the EDK subdirectory and reopening the new project (system.xmp), we will add the generated and exported hardware module (which is called fsl_des) to the platform and create the necessary bus connections. We'll begin by adding the new IP core.

Adding the 3DES Hardware IP Core

To add the new IP core, we select Project -> Add/Edit Cores to bring up the dialog box shown in Figure 9-11. This dialog lists all the available IP cores, most of which are provided as standard with the Xilinx EDK distribution. We will be making use of two additional cores in this example (apart from the MicroBlaze and related cores that were already added by Base System Builder): The newly generated encryption core (fsl_des) and a timer core (opb_timer) that will be used to obtain actual timing information for our test.

Figure 9-11. Adding the generated hardware block as a peripheral.

To add the fsl_des core, we select it from the list as shown and click the Add button. The fsl_des module now appears in the list of peripherals on the left side of the dialog box.

Setting the FSL Bus Parameters and Connections for the Core

Next, we need to set some parameters related to this hardware process, setting up the communication with the FSL bus. We click the Parameters tab in the Add/Edit dialog, then add the C_FSL_LINKS parameter by selecting IP instance microblaze_0 and selecting parameter C_FSL_LINKS. We then click the Add button to add the parameter. After adding the C_FSL_LINKS parameter, we set its value to 3, indicating that the hardware process will require three FSL connections, one for each stream as shown in Figure 9-12.

Figure 9-12. Specifying the number of FSL links.

Next, we click the Bus Connections tab to open the Bus Connections page. We select fsl_v20_v1_00_b and click Add three times to create three new bus connections. We specify the new bus connections as follows:

microblaze_0 mfsl0 connects to fsl_v20_0

microblaze_0 mfsl1 connects to fsl_v20_1

microblaze_0 sfsl2 connects to fsl_v20_2

fsl_des_0 sfsl0 connects to fsl_v20_0

fsl_des_0 sfsl1 connects to fsl_v20_1

fsl_des_0 mfsl2 connects to fsl_v20_2

The completed bus connections are shown in Figure 9-13.

Figure 9-13. Connectng the new peripheral to the FSL links.

We now select the Ports page by clicking the Ports tab. We add the clk and co_clk ports as internal ports under fsl_des_0. We also change the net name for port co_clk to sys_clk_2 as shown in Figure 9-14. This reflects the fact that we are creating a dual-clock system, in which the FPGA component (our hardware encryption algorithm) will run at a different clock rate than the MicroBlaze processor. Synchronization across clock domains is handled automatically by the dual-clock FIFO interfaces that were generated for us by the Impulse compiler. (Note: If co_clk is missing from the fsl_des_0 section at this point, we have probably set the hardware generation options incorrectly in the Impulse tools and have generated a single-clock interface.)

Figure 9-14. Adding the clock and reset lines for the new peripheral.

Now we need to add the external port for the secondary clock, which in this case of the Memec development board chosen is a 24MHz clock. We do this by selecting the co_clk entry in the Internal Ports Connections and clicking the Make External button, as shown in Figure 9-15. As specified, the MicroBlaze processor runs at 100MHz while the FPGA logic implementing the encryption algorithm operates at 24MHz.

Figure 9-15. Adding a second external clock (sys_clk_2).

Remaining on the Ports page, we now connect the clocks for the three created FSL bus connections (fsl_v20_0, fsl_v20_1, and fsl_v20_2). For each of these bus connections, we add the FSL_Clk and SYS_Rst ports, as shown in Figure 9-16.

Figure 9-16. Adding clock and reset signals for the FSL links.

For each FSL link, we set FSL_Clk to sys_clk_s. We also set SYS_Rst to net_gnd as shown, and we set the clk port for fsl_des_0 to sys_clk_s, as shown in Figure 9-17.

Figure 9-17. Renaming the fsl_des_0 clock net name.

Adding and Configuring an OPB Timer Core

Now we need to add the OPB timer core. This timer will be used to time the software and hardware implementations of the 3DES algorithm so we can do a rough performance comparison. To add the timer core, we select the Peripherals tab of the Add/Edit dialog and choose opb_timer from the list of IP cores as shown in Figure 9-18. We then select the Bus Connections tab and connect the opb_timer_0 core to the mb_opd bus, as shown in Figure 9-19.

Figure 9-18. Adding an OPB timer peripheral.

Figure 9-19. Connecting the OPB timer peripheral.

Last, we select the Ports tab and add the OPB_Clk port under opb_timer_0, setting OPB_Clk to sys_clk_s as was done for the fsl_des_0 clock ports.

Specifying the Peripheral Addresses

Now we need to set the addresses for each of the peripherals specified for the platform, including the opb_timer just added. This is done by choosing the Addresses tab of the Add/Edit dialog and clicking the Generate Addresses button. The addresses are assigned automatically by Platform Studio (see Figure 9-20). Notice that the fsl_des peripheral is not listed here because it is not connected to the OPB.

Figure 9-20. Setting peripheral and memory addresses.

Specifying the System Clock Pin

Now we need to add a second system clock pin to the system, representing the 24MHz clock that will drive our encryption peripheral. In the system view of the Platform Studio project, we double-click the system.ucf file (located under Project Files) then add the following line:

 Net sys_clk_2 LOC=A11; 

The specified pin (A11) represents the 24MHz clock provided on the Memec board used in this example. (The clock pin on other target boards may be different.)

We have now exported all necessary hardware files from the Impulse tools to the Xilinx tools environment and have configured the new platform. The next step is to import the software source files representing the test bench that will run on the MicroBlaze processor.

Importing the Application Software

Now we will import the relevant software source files to the Platform Studio project. To do this, we click the Applications tab of the project to view the sample project named TestApp (see Figure 9-21). This sample application was generated automatically by Base System Builder when we created the project.

Figure 9-21. Modifying the sample application generated by Base System Builder.

We delete the automatically generated sample source file (TestApp.c) from the Project Sources and then right-click Sources under microblaze_0 and select Add Files. A file selection dialog appears. We navigate to the code directory and select the two files shown in Figure 9-22 (des_sw.c and co_init.c), clicking Open to add the source files to the project. These files comprise the software application that will run on the MicroBlaze CPU. (The des.h and sp.c files are included indirectly through the use of include statements in the des_sw.c file.)

Figure 9-22. Importing the software test bench files.

The complete hardware/software application is now ready to be synthesized, placed, and routed to create a downloadable FPGA bitmap. The next section describes how to create the final bitmap, download the bitmap to the device, and run the test application.

Generating the FPGA Bitmap

We are now ready to generate the bitmap and download the complete application to the target platform. First, from within Platform Studio we select the Generate Bitstream item from the Tools menu (see Figure 9-23). This process requires about one hour to complete on our Windows development system.

Figure 9-23. Generating the FPGA bitmap.

The generated bitstream includes the FPGA image representing our encryption processes (fsl_des) as well as the MicroBlaze processor core and its various peripherals, including the UART core needed for the RS232 port, the SRAM controller, and the OPB timer peripheral. It does not yet, however, include the binary image for the software that will run on the MicroBlaze processor.

To generate the required software binary image, we must first select the Build All User Applications menu item, shown in Figure 9-24. This triggers a compile and link of des_sw.c, co_init.c, and related library files.

Figure 9-24. Building the MicroBlaze software application.

After the compilation is complete, we add the compiled binary image to the FPGA image by selecting the Update Bitstream menu item, as shown in Figure 9-25. This menu item adds the software binary image to the FPGA bitmap file. We are now ready to download and execute the application.

Figure 9-25. Updating the bitstream with the compiled application files.

Downloading and Running the Application

Before downloading the application to the target board and FPGA, we open a Windows HyperTerminal session connecting our development machine to the serial port connected to the RS232 peripheral on the main FPGA development board. We use the same communication settings we chose when defining the RS232 peripheral in Base System Builder (9600 baud, 8 bits, no parity).

The RS232 cable is attached, as is the parallel port FPGA download cable. We turn on the power to the board, then select the Download function from the Tools menu in Platform Studio. A series of messages appears in the Platform Studio transcript, and after the FPGA has been successfuly programmed we see (on the Hyperterminal window) a series of messages generated by our software test bench through the use of printf statements. These messages indicate that the test was successful, and report the time required to perform the test encryption in both software and hardware, as shown in Figure 9-26.

Figure 9-26. Downloading and executing the test application.

    Practical FPGA Programming in C
    Practical FPGA Programming in C
    ISBN: 0131543180
    EAN: 2147483647
    Year: 2005
    Pages: 208 © 2008-2017.
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