Chapter 9. Creating an Embedded Test Bench
The latest generation of FPGAs featuring hard or soft embedded processors offer compelling platforms for hardware acceleration of computationally intensive software algorithms. Design teams taking advantage of these platforms are finding that a combination of traditional software applications running on the embedded processor and custom accelerators implemented within the FPGA fabric are an efficient way to create high-performance products and prototypes.
One important and often overlooked benefit of using a combination of embedded processors and hardware accelerators is the ability to create embedded software/hardware test fixtures, or test benches. By using such an approach in conjunction with a streaming programming model, it is possible to verify the correct operation of a hardware module (at least in terms of its functional behavior, if not its timing characteristics) with a high level of accuracy relative to the speed at which new tests can be developed.
Embedded test benches are therefore the subject of this chapter. To describe some potential ways in which these test benches may be written, we will continue with our discussion of the triple-DES algorithm presented in the preceding chapter.