Router Architecture


Each router consists of two major architectural components : the Routing Engine and the Packet Forwarding Engine.

In each Juniper Networks router, the router architecture cleanly separates routing and control functions from packet forwarding operations, eliminating bottlenecks and permitting the router to maintain a high level of performance. Each router consists of two major architectural components: the Routing Engine, which provides Layer 3 routing services and network management, and the Packet Forwarding Engine, which provides Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding.

The Routing Engine and Packet Forwarding Engine perform their primary tasks independently, while constantly communicating through a high-speed internal link. This arrangement provides streamlined forwarding and routing control and the capability to run Internet-scale networks at high speeds. Figure 3.1 illustrates the relationship between the Routing Engine and the Packet Forwarding Engine.

Figure 3.1. Router Architecture

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For more information about the Routing Engine, see "Routing Engine" on page 37.

The Routing Engine consists of an Intel-based PCI platform running JUNOS Internet software. The Routing Engine maintains the routing tables used by the router and controls the routing protocols that run on the router. For more information about the JUNOS Internet software that runs on the Routing Engine, see Chapter 2, "JUNOS Internet Software Overview."

The Routing Engine constructs and maintains one or more routing tables. From the routing tables, the Routing Engine derives a table of active routes, called the forwarding table, which is then copied into the Packet Forwarding Engine. The design of the Internet Processor II and T-series Internet Processor ASICs allows the forwarding table in the Packet Forwarding Engine to be updated without interrupting forwarding performance (see Figure 3.2).

Figure 3.2. Control Packet Handling: Routing and Forwarding Table Updates

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The Packet Forwarding Engine uses ASICs to perform Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding. On M-series routers, the Packet Forwarding Engine includes the router midplane (on an M40 router, the backplane), Flexible PIC Concentrators (FPCs), Physical Interface Cards (PICs), and other components, unique to each router, that handle forwarding decisions.

Packets enter the router through incoming PIC interfaces, which contain controllers that perform media-specific processing. The PICs pass the packets to the FPCs, where they are divided into cells and distributed to the router's shared memory. The Packet Forwarding Engine performs route lookups, forwards the notification to the destination port, reassembles the cells into packets, and sends them to the destination port on the outgoing PIC. The PIC performs encapsulation and other media-specific processing, and sends the packets out to the network.

Figure 3.3 illustrates the flow of data packets through an M-series router, using the M40e router architecture as an example. In this example, a packet enters through the incoming PIC, which parses and de-encapsulates the packet, then passes it to the FPC. On the FPC, the Packet Director ASIC distributes packets among the I/O Manager ASICs, where each is divided into cells and sent across the midplane to the SFMs.

Figure 3.3. Data Flow through an M40e Router

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When cells arrive at an SFM, the Distributed Buffer Manager ASIC writes them into packet buffer memory, which is distributed evenly across the router's FPCs. The Distributed Buffer Manager ASIC also extracts information needed for route lookups and passes the information to the Internet Processor II ASIC. The Internet Processor II performs the lookup in the full forwarding table, finding the outgoing interface and specific next hop for each packet. The forwarding table can forward all unicast packets that do not have options and multicast packets that have not been previously cached. Other packets are sent to the Routing Engine for resolution.

After the Internet Processor II ASIC has determined the next hop, it notifies a second Distributed Buffer Manager ASIC, which forwards the notification to the outgoing FPC. A pointer to the packet is queued at the outgoing port. When the packet pointer reaches the front of the queue and is ready for transmission, the cells are read from packet buffer memory and reassembled into the packet, which is passed to the outgoing PIC interface. The PIC performs media-specific processing and sends the packet to the network.

The T-series routing node features multiple Packet Forwarding Engines, up to a maximum of 16. On the T-series routing node, the Packet Forwarding Engines are contained on the FPCs. Each FPC has one or two Packet Forwarding Engines, each with its own memory buffer. Each Packet Forwarding Engine maintains a high-speed link to the Routing Engine.

Figure 3.4 shows the data flow through a T640 routing node. Packets enter through an incoming PIC and are passed to the Packet Forwarding Engine on the originating FPC. The Layer 2/Layer 3 Packet Processing ASIC parses the packets and divides them into cells. The network- facing “Switch Fabric ASIC places the lookup key in a notification and passes it to the T-series Internet Processor. The Switch Fabric ASIC also passes the data cells to the Queuing and Memory Interface ASICs for buffering on the FPC. The T-series Internet Processor ASIC performs the route lookup and forwards the notification to the Queuing and Memory Interface ASIC.

Figure 3.4. Data Flow through a T640 Routing Node

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The Queuing and Memory Interface ASIC sends the notification to the switch-fabric “facing Switch Interface ASIC, which sends bandwidth requests through the switch fabric to the destination port and issues read requests to the Queuing and Memory Interface ASIC to begin reading data cells out of memory. The Switch Interface ASIC on the destination FPC sends bandwidth grants through the switch fabric to the originating Switch Interface ASIC. Upon receipt of each grant, the originating Switch Interface ASIC sends a cell through the switch fabric to the destination Packet Forwarding Engine.

On the destination Packet Forwarding Engine, the switch-fabric “facing Switch Interface ASIC receives the data cells, places the lookup key in a notification, and forwards the notification to the T-series Internet Processor. The T-series Internet Processor performs the route lookup and forwards the notification to the Queuing and Memory Interface ASIC, which forwards it to the network-facing Switch Interface ASIC. The Switch Interface ASIC sends requests to the Queuing and Memory Interface ASIC to read the data cells out of memory and passes the cells to the Layer2/Layer 3 Packet Processing ASIC, which reassembles the cells into packets, performs the necessary Layer 2 encapsulation, and sends the packets to the outgoing PIC. The PIC passes the packets into the network.



Juniper Networks Field Guide and Reference
Juniper Networks Field Guide and Reference
ISBN: 0321122445
EAN: 2147483647
Year: 2002
Pages: 185

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