4.9 Addressing in Other Architectures

The Itanium EPIC architecture implements roughly the same number of addressing modes as RISC architectures. CISC architectures, however, offer a greater variety of addressing modes, some of which we will briefly describe.

4.9.1 Modes Built on Register Indirect Addressing

The VAX, as quintessential CISC architecture, provides an opportunity for contrast because it includes three variants of register indirect addressing:

Register Indirect	(Rx)	Effective address = contents of Rx
Autoincrement	(Rx)+	Effective address = contents of Rx
		Rx is then advanced to the next information unit
Autodecrement	-(Rx)	Rx is moved back to the previous information unit
		Then effective address = contents of Rx

The computer adjusts the register by the size of the information unit accessed (byte, word, etc.). These modes allow sequential accessing of elements in arrays and stacks.

The progression from immediate to register direct to register indirect addressing involves increasing both complexity in addressing and, more seriously, the number of cycles required to retrieve data. This progression of modes could be extended another degree beyond register indirect addressing, if the first information unit from memory contained not the real data but rather another pointer (effective address) leading finally to the data. This mode has been called register indirect deferred addressing. VAX architecture has an addressing mode called autoincrement deferred, with the assembler syntax @(Rx)+. The contents of the register represent the address of a memory unit, which in turn contains the effective address of a specified datum. After serving as pointer-to-the-pointer, the register is automatically advanced by one double word. This mode is useful for algorithms that involve lists of address pointers, such as tag sorts, or passing arguments to external procedures by address.

4.9.2 Modes Built on Displacement Addressing

Powerful addressing modes compute the effective address by combining the contents of a register with a constant called a displacement. The instruction must contain bits to designate the register and to specify the displacement. Displacement mode has also been called base addressing in architectures where particular registers are called base registers. The assembler syntax for displacement addressing is disp(Rx). RISC architectures (e.g., Alpha) use displacement addressing only for load, store, and jump instructions.

Many architectures conveniently offer a form of symbolic direct addressing that is implemented as displacement addressing using the program counter (PC) as the base address:

opcode symbol is equivalent to opcode disp(PC)

where the assembler and linker assure that the displacement measures the addressing "distance" between this instruction and the datum at the location denoted by symbol. This is also called relative addressing because, after linking, all data locations can be located by displacements relative to the program counter. This method of addressing also occurs in branch, jump, and call instructions in the Itanium architecture and many others.

A few other RISC architectures, and some CISC architectures, implement not only this addressing mode but also a mode called relative addressing deferred:

opcode @symbol is equivalent to opcode @disp(PC)

where a pointer is read from the memory location symbolized by disp(PC) and then used as the effective address.

4.9.3 Comparison of Modes Across Architectures

Table 4-5 summarizes the occurrence of the modes we have discussed for a 32-bit CISC design (VAX), a rather pure RISC design (Alpha), and the new EPIC design (Itanium).

Table 4-5. Addressing Modes for Various Architectures

Mode	Syntax	VAX	Alpha	Itanium
Immediate	imm	Yes	Integer operations	Integer operations
Register direct	Rx	Yes	Yes	Yes
Register indirect	(Rx)	Yes	Displacement = 0	Yes
Displacement	disp(Rx)	Yes	Load, store, jump	Branch
Displacement deferred	@disp(Rx)	Yes	No	No
Autoincrement	(Rx)+	Yes	No	No
Autodecrement	-(Rx)	Yes	No	No
Autoincrement deferred	@(Rx)+	Yes	No	No
Relative	addr(PC)	Yes	No	No
Relative deferred	@addr(PC)	Yes	No	No
Other modes		Yes	No	No

Short sequences of Itanium instructions can readily emulate some of the more complicated addressing modes. Autoincrement deferred mode can be accomplished as follows:

 ld8  Rdest = [Rpointer],8;; ld8  Rdest = [Rdest] 

where Rpointer is a selected index register and Rdest can hold the intermediate address pointer and later receive the data value. A RISC-like computer has a performance advantage if it can execute such sequences of simpler instructions in a shorter overall time than is required for the corresponding single complex instruction of a CISC computer.