Summary

We have presented a generic layout for Itanium machine instructions in this chapter and introduced the unique aspect of bundling three adjacent instructions, along with a template, into 128 bits. We deferred explaining the role of templates in decoding instructions and executing them in parallel.

This chapter illustrated the usage of three important groups of instructions for integer data: basic arithmetic, load and store, and sign control. Two sample programs illustrated these instructions, as a foundation for building more complex and realistic algorithms.

Throughout the chapter, we discussed the standard architectural concepts of addressing, especially the concept of effective address as an aid in classifying the various modes. This required introducing the related topic of temporal locality, which most simply is the relative proximity of the data to the CPU as given by the number of access steps to fetch the data.

The chapter ended with a brief overview of additional addressing modes used in other computer architectures, with an emphasis on the role of registers. Indeed, the simple set of modes of the Itanium architecture should perform well in conjunction with the very large register set and EPIC features.