| 1: | Discuss why the three principal structures of a computer system are largely invisible to a high-level language programmer. |
| 2: | Is the bus a part of a computer's architecture? Why, or why not? |
| 3: | What is an address? In Figure 2-2, the last address is given as N 1. Why? If a memory unit has an address 37 (base 10), how many memory units precede it? |
| 4: | Compare and contrast a computer memory system to the human memory. |
| 5: | What is the address space? How is the size of the address space determined? If a machine has a 4-bit address, how many addressable memory units are there? How are they numbered? |
| 6: | If we wish to run a program with 69,326 bytes of instructions and data on a hypothetical computer, what does this imply about the size of addresses (in bits) needed on the computer? |
| 7: | What are the parts of an instruction? Describe in detail the steps in the execution of an instruction. Why are instructions stored (and executed) sequentially in memory? Can you think of an alternative? |
| 8: | You have seen the CPU execution cycle: Instructions are fetched from sequential memory locations and executed, one after another, until a branch or change of control occurs. Can you imagine a machine in which instructions are not fetched sequentially? How would such a machine function? What would its instructions look like? Would it be "fun" to program? |
| 9: | How many different memory addresses can be encoded in a 44-bit physical address supported by the first Itanium processor? Repeat for the 50-bit physical address supported by the Itanium 2 processor. |
| 10: | Although the Intel386 chip and its successors are designed to address only 4 GiB of physical memory (Table 1-3), they have a way of combining bits from two registers in order to generate a virtual address space of 64 TiB. What is the total number of bits needed to do that? |
| 11: | Although the Hewlett-Packard PA-RISC 8xxx processors ordinarily use 64-bit virtual addresses, they retain some 32-bit "space ID" registers from the 7xxx processors that may be concatenated to produce a 96-bit address space. Compute the approximate number of 96-bit addresses. |
| 12: | What are the information units for the Itanium architecture? What distinguishes an information unit from a data type? What are the Itanium data types and what is each data type used for? |
| 13: | A binary fraction is normalized if it begins with a one (the value of the fraction is then at least one-half). Why are normalized fractions used in floating-point number representations? |
| 14: | Show the hexadecimal IEEE single-precision representation in memory for the decimal value 2.5. Show the hexadecimal IEEE single-precision representation for the decimal value 2.6. Which was harder to compute? Why? |
| 15: | Repeat exercise 2.14 using IEEE double-precision representation. |
| 16: | What is the largest odd integer that can be represented exactly in IEEE single-precision format in memory? |
| 17: | Explain why UTF-8 does not need to have big-endian and little-endian variants. |
| 18: | Show the ASCII representation for this sentence. |
| 19: | If the M of My Itanium is stored in a byte with address 1246 (hex), known symbolically as STRING, what is the address of the byte containing the m? |
| 20: | What relationship exists between the value of a numeral and its representation as an ASCII character? |
