The earliest servers used DRAM. The fastest DRAM speed was 60ns. The lower the ns rating, the faster the memory. (This can be confusing if you're accustomed to the newer method of expressing memory speeds in MHz or throughput [MBps].) A nanosecond is defined as one billionth of a seconda very short time indeed. To put some perspective on that, the speed of light is 186,282 miles (299,792 kilometers) per second in a vacuum. In one billionth of a second, a beam of light travels a mere 11.80 inches, or 29.98 centimetersless than the length of a typical ruler! To convert access time in nanoseconds to MHz, you use the following formula:
To convert from MHz to nanoseconds, you use the following inverse formula:
Although 60ns might seem very fast, it converts to about 16.7MHz, or less than 1/100 of the speed of recent server processors. Standard DRAM was used in servers up through about 1998. A slightly faster form of DRAM, known as extended data out (EDO) DRAM, was developed in the mid-1990s and was used in some servers as well. Although EDO DRAM's clock speed was also 60ns, it had improved memory access internally, to provide slightly faster throughput. When we compare the speed of typical server processors in the mid-1990s to DRAM or EDO DRAM memory, it's obvious that the memory was actually slowing down system performance. For example, consider a Pentium Pro processor running at 200MHz. 200MHz is equivalent to 5ns. In other words, the processor was 12 times faster than memory (60/5=12)! With faster processors in use by 19961997, such as the Pentium II and the Pentium II Xeon, the mismatch between processor speed and memory speed became even more lopsided. For example, a 300MHz Pentium II runs at the equivalent of 3.3nsmore than 18 times faster than the 60ns memory used in early models! By 2000, servers were using memory types based on a new standard, called SDRAM (synchronous DRAM). 100MHz memory (PC100) and 133MHz memory (PC133) were the most common. Starting in early 2001, double data rate (DDR) memory of 200MHz and 266MHz become popular, along with 800MHz Rambus DRAM (RDRAM). In 2002, standard 333MHz DDR memory arrived, and in 2003, the speeds increased to 400MHz. The fastest current memory is DDR2, now available at 400MHz, 533MHz, 667MHz, and 1000MHz. System memory timing is a little more involved than simply converting nanoseconds to megahertz. The transistors for each bit in a memory chip are most efficiently arranged in a grid, using a row-and-column scheme to access each transistor. All memory accesses involve selecting a row address and then a column address and then transferring the data. The initial setup for a memory transfer where the row and column addresses are selected is a necessary overhead referred to as latency. The access time for memory is the cycle time plus latency for selecting the row and column addresses. For example, SDRAM memory rated at 133MHz (7.5ns) typically takes five cycles to set up and complete the first transfer (5x7.5ns = 37.5ns) and then perform three additional transfers with no additional setup. Thus, four transfers take a total of eight cycles, or an average of about two cycles per transfer. Over the development life of the PC, memory has had a difficult time keeping up with the processor, requiring several levels of high-speed cache memory to intercept processor requests for the slower main memory. Table 5.3 shows the progress and relationship between system board (motherboard) speeds in servers and the most common types and speeds of main memory or RAM used and how these changes have affected total bandwidth.
Generally, a system works best when the throughput of the memory bus matches the throughput of the processor bus. Compare the memory bus transfer speeds (bandwidth) to the speeds of the processor bus shown in Table 5.4, and you see that some of the memory bus rates match some of the processor bus rates. In most cases, the type of memory that matches the CPU bus transfer rate is the best type of memory for systems with that type of processor.
Because the processor is fairly well insulated from directly dealing with main memory by the L1 and L2 caches, memory performance has often lagged behind the performance of the processor bus. Systems using RDRAM, SDRAM, DDR, and DDR2 SDRAM have memory bus performance equaling that of the processor bus. When the speed of the memory bus equals the speed of the processor bus, memory performance is optimum for that system. |