PowerTheater Analyst, built with proven Watt Watcher technology, represents a superior alternative to tedious and error-prone manual methods , such as spreadsheet analysis, as well as gate- and transistor -level methods which require the design to be synthesized in pieces and then simulated at very detailed levels of abstraction. Using this capability at both RT and gate level, designers can perform detailed power analysis for the entire chip or any set of sub-blocks, including memory, I/O, logic, and clock trees. Peak and time-based power is reported on a user -defined time interval, down to the Verilog or VHDL simulation resolution. PowerTheater Analyst addresses issues such as power bus sizing, electromigration, and reliability at the RT level, before the design is synthesized .
Accurate RTL power estimation helps designers minimize power early in the design cycle.
Versatile graphical analysis environment lets designers assess trade-off options quickly and intuitively.
Peak and time-based power analysis allows designers to pinpoint power problems and understand the details of power consumption.
Vector analysis capability to determine vector coverage and testbench quality.
Fast, high-capacity RTL, gate, and mixed full-chip analysis for multimillion-gate designs covers all major contributors of power dissipation including:
Clocks, including built-in clock-tree estimation
Memory, including single and multiport SRAM and DRAM
Data path and control logic
I/O, including multiple voltage
Supports Verilog, VHDL, and mixed-language analysis.
Incremental compile and split activity file processing increase analysis performance and capacity.
Comprehensive detailed reports in formatted text and HTML.