Section 4.3. Power-On Reset

4.3. Power-On Reset

When a PowerPC-based Apple computer system is powered on, a power-on reset (POR) unit handles the "coming to life" of a processor. On the 970FX, the POR sequence consists of seven phases tracked by hardware state machines. The sequence involves communication between the processor core, the North Bridge (the U3H), and a custom microcontroller. During the sequence, the processor is initialized by a hardcoded set of instructions, which also run certain tests and synchronize the processor-interconnect interfaces. In the third phase of the POR sequence, the hardware interrupt offset register (HIOR) is initialized. The HIOR is used for interrupt vector relocation: It defines the base physical address for the interrupt vectors. In the last phase, the processor's storage subsystem clock is started and the storage interface is reset. At this point, the processor starts fetching instructions at the system reset exception vector. The system reset exception is a nonmaskable, asynchronous exception that has the highest priority of all exceptions. It causes the processor's interrupt mechanism to ignore all other exceptions and generate a non-context-synchronizing interruptthe system reset interrupt (SRI).

Machine Check Exception

Another example of a nonmaskable, asynchronous exception is the machine check exception (MCE). It can only be delayed by a system reset exception.

The handler for the SRI is the first entry in the PowerPC interrupt vector table. Its effective address is calculated by combining its vector offset, which is 0x100, with certain bits of the HIOR. Thus, the processor core resumes execution at HIOR + 0x0000_0000_0000_0100. At power-on, the SRI handler, and any others in the table, all belong to Open Firmware, which is in control of the processor. At this point, the processor is in real address modethat is, memory translation is disabled (an effective address is the same as a physical address). Moreover, the processor caches are disabled.

Note that a system reset exception could be due to a hard or a soft reset. A hard resetsuch as one due to a real PORis seen only by Open Firmware. In contrast, the Mac OS X kernel will see only a soft resetregardless of whether the processor is being brought up after a POR or is waking up from sleep.

On a multiprocessor system, Open Firmware selects one processor, using a suitable algorithm, to be the master processor, which is then responsible for booting the client and providing the Open Firmware user interface. The other processors are typically stopped so they do not interfere with the master processor.