2.8 Computer architectures

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2.8 Computer architectures

To continue our earlier discussion of computer configurations we will examine how the various components can be interconnected to form a computer system. The basic premise of these architectures is to speed up the movement of data to allow for increased processing. The basic architecture has the CPU at the core with a main memory and input/output system on either side of the CPU (see Figure 2.12). In this architecture all data flows into, out of, and through the CPU under the control of the CPU. This represents the basic von Neumann architecture described earlier. Refinements of this architecture have been designed to remove the CPU from the burden of controlling all data movement.

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Figure 2.12: Basic computer architecture.

2.8.1 Central I/O controller architectures

To remove the CPU from the central function of coordinating all data flow the central input/output controller architecture was developed (see Figure 2.13). This architecture has the IOC at the core of the system with the CPU, main memory, and I/O devices connected to the IOC hub. To transfer data from the main memory to an I/O device the CPU would command the IOC to initiate the transfer. The data would flow under control of the IOC from the main memory through the IOC to the named output device. The problem with this architecture is that the CPU must also use the IOC to transfer data from the main memory to the CPU. This results in potential reduction in CPU performance. Variations of this architecture have a secondary path to the main memory for better service to the CPU.

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Figure 2.13: Computer architecture utilizing an I/O controller.

2.8.2 Memory-mapped architectures

The main memory is the location in the computer system where all data and instructions flow in and out. As a consequence of this, an architecture was proposed that had the main memory as the central element (see Figure 2.14). The main memory sits between the CPU and I/O. All data flow between the I/O and CPU goes through the memory. A variety of control schemes have been devised to control the access to the shared memory. One is to partition the memory into regions: one region for the CPU to use and one for each of the I/O devices on the system. To send data to an I/O device the CPU simply addresses the memory location for the device. By doing this the device's input register is directly loaded with the data. To the CPU the I/O transfer is the same as a write to main memory.

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Figure 2.14: A computer system organized around memory.

2.8.3 Common bus architecture

An architecture that is similar to the global network architecture previously described is the unibus architecture. The unibus or global bus architecture uses a single communications bus to interconnect memory, CPU, and I/O devices (see Figure 2.15). These elements are connected to the bus and communicate with each other using addresses over the bus. As in the network case, this design will result in reduced utilization if conflicts between bus accesses are frequent. This architecture was successfully used in numerous early digital equipment computers and is still in use in many systems.

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Figure 2.15: Unibus architecture.

2.8.4 Dual bus architecture

A refinement on the single bus architecture is the dual bus architecture (Figure 2.16). In this architecture the central hub of the computer is a dual bus configuration: one bus for memory traffic and one for I/O traffic. All devices, CPU, main memory, disks, tapes, terminals, and direct memory access devices are connected to both buses. This architecture removed some of the contention between the CPU memory accesses and I/O transfers. The CPU and memory were free to actively move data to and from memory, as were the I/O devices, without conflict. An I/O device could be writing into one region of memory while the CPU was concurrently accessing another section. Architectures that have derived from this philosophy are more common in modern computer systems. We will see how these architectures and elements of the computer system are used by database management systems as we continue with our discussion of database management system architectures and operations.

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Figure 2.16: Dual bus architecture.



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Computer Systems Performance Evaluation and Prediction
Computer Systems Performance Evaluation and Prediction
ISBN: 1555582605
EAN: 2147483647
Year: 2002
Pages: 136

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