Summary

This chapter has contained several types of interwoven material, concepts, and methods of analysis of assembly language programs. We began with a general discussion about control of flow in programs, which has formed an underlying theme throughout the chapter.

We then introduced the simplest forms of the Itanium integer compare instructions, their completers for testing equality and signed or unsigned inequality, and their use for setting Boolean predicate register values both normally and "unconditionally."

We also introduced two forms of the Itanium branch instructions, predicated conditional branches (with the unconditional branch as a special case using predicate register Pr0) and a special unpredicated form that operates in conjunction with the architectural loop counter register for controlling loops.

We discussed the use of predication, with or without associated branches, for the implementation of many standard types of programming constructs. In doing so, we have pointed out how the Itanium architecture offers opportunities to eliminate branch instructions that would be present in code for traditional architectures.

We presented a simplified view of Itanium instruction latency and the relationships among latency, instruction groups, instruction bundles, and available execution units. We shall develop that material in greater depth in a later chapter.

Knowledge of how branch instructions work has opened up a wider universe of still-simple algorithms for example programs and exercises. Three Itanium assembly language programs have illustrated some of the major ideas and techniques of this chapter and will provide a basis for some of the exercises.



ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ISBN: N/A
EAN: N/A
Year: 2003
Pages: 223

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