Coprocessor instructions

Each SPARC Version 8 implementation that utilizes the optional coprocessor unit must define its own instructions. However, there are two instruction opcodes reserved for coprocessor instructions:

Table B-24. Instruction opcodes reserved for coprocessor instructions

Opcode	Recommended Instruction Syntax
COop1	cpop1 opc, screg 1 , screg 2 , dcreg
COop2	cpop2 opc, screg 1 , screg 2 , dcreg

opc would represent the specific operation, two source registers screg1 and screg2 could be specified, and of course, there would be a destination register, dcreg . All of the registers would reside on the coprocessor.

The coprocessor instructions can generate cp exception and cp disabled traps.