3.2 1Gbps and 2Gbps Transport

To move data bits with integrity over a physical medium, a reference clock must be provided to ensure that each bit is received as it was transmitted. In parallel topologies, a separate clock or strobe line serves this function. As data bits are launched in parallel from the source, the strobe line toggles high or low to signal the receiving end that a full byte (or multiple bytes for 16- and 32-bit wide parallel cabling) has been sent.

Because serial data transports can have only two lines (transmit and receive), clocking cannot be achieved by a separate line. The serial data itself must carry the reference timing; in other words, clocking must be embedded in the bit stream. Different serial transports accomplish embedded clocking by different means. Fibre Channel uses a byte encoding scheme and CDR (clock and data recovery) circuitry to recover clock and thus determine the data bits that compose bytes and words.

At gigabit speeds, maintaining valid signaling (and therefore valid data recovery) is critical for data integrity. Fibre Channel standards allow for a single bit error to occur only once in a trillion bits (10 ¹²). In practice, this amounts to a maximum of one bit error every 16 minutes, although actual occurrence of bit errors is far less frequent. One of the challenges for Fibre Channel vendors is to improve on this bit error rate. Reducing the rate to 10 ¹³ would reduce statistical occurrence to one bit error every 2.5 hours. Such reductions are possible if attention is given to the hardware interface design, cable quality, cable length, and the system's jitter budget.

Jitter refers to any deviation in timing that a bit stream suffers as it traverses the physical medium and the circuitry on-board the end devices. A certain amount of deviation from the original signaling will occur naturally as a serial bit stream propagates over fiber-optic or copper cabling. Signaling can also be affected by transients from power supplies, board design, and other sources of electromagnetic interference (EMI). Recognizing that jitter cannot be eliminated, Fibre Channel standards have attempted to set guidelines for how much jitter individual components can contribute. If each product abides by the recommended jitter budget, timing deviations to gigabit signaling with a system should not exceed the recommended bit error rate of 10 ¹².

Measuring the jitter contribution of any component requires expertise and expensive equipment. Because test equipment itself may contribute to jitter, research for better techniques and test facilities is ongoing. The ANSI T11.2 Methodologies for Jitter Specification (MJS) group is one official body that is attempting to define valid, unintrusive methods for measuring and defining jitter limits.

Jitter is typically represented in graphical form by an eye diagram on a test scope, as illustrated in Figure 3-1. The cross-over points or intersections forming the "eye" represent signaling transitions to high or low voltages. Ideally, all transitions should occur at precisely the same interval. If that were the case, the clock and data recovery circuitry could recover all data bits with no bit errors whatsoever. In reality, some deviation will always be observed. If the jitter is too extreme, the CDR will miss one or several bits, resulting in the corruption of Fibre Channel words or data within frames.

Figure 3-1. Eye diagram showing signal transitions that may result in bit errors

Jitter is an important element in SAN design because every component can potentially contribute to jitter or jitter accumulation. A faulty transceiver, substandard fiber-optic cabling or connectors, cable distances that exceed guidelines, improperly shielded copper components, or simply bad product design can introduce system instability at the physical layer. Despite what you will read in the marketing material of some vendors, no Fibre Channel product is jitter-free. Consequently, selection of low-jitter components should be based, when possible, on independent verification in addition to the vendor's product specification.

Because 2Gbps Fibre Channel doubles the clock rate of 1Gbps Fibre Channel, it is essential to maintain signal integrity through the cable plant and SAN equipment. Fortunately, vendors have been able to apply their considerable experience with 1Gbps jitter issues to produce stable 2Gbps products. In addition, the installed base of 1Gbps Fibre Channel products has required support for auto-negotiation circuitry on 2Gbps Fibre Channel switches and HBAs. When a 1Gbps device is plugged in to a 2Gbps switch port, for example, the CDR of the switch port senses the incoming clock and automatically adjusts its own baud rate. This enables a mix of 1Gbps and 2Gbps products in the same SAN. In addition to end devices, 2Gbps capability is useful for maximizing throughput of interswitch links.