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3.3 Time Response in Combinational Networks

Our analysis of circuits so far has concentrated on the static behavior of combinational networks. The analysis adequately describes a circuit in steady state, but it is not enough to tell us about a circuit's dynamic behavior. Remember that the propagation of signals through a network is not instantaneous. This characteristic can be useful, for example, when creating circuits that output pulse signals. But it causes problems if the momentary changes of signals at the outputs lead to logical errors. Such transient output changes are called glitches. A logic circuit is said to have a hazard if it has the potential for these glitches. We'll discuss glitches and hazards in Section 3.4.

As a hardware designer, it is extremely important to be able to visualize the behavior of a circuit as a function of time-that is, to be able to look at a circuit and see how signals move through it, recognizing asymmetric delays along paths that can lead to transitory behavior at the outputs. This is not an easy skill to acquire, even after extensive design experience. Fortunately, simulation tools can offer great assistance in visualizing the time-based behavior of circuits.

3.3.1 Gate Delays

Outputs in combinational logic are functions of the inputs and some delay. As we stated in Chapter 2, gate delay is the amount of time it takes for a change at the gate input to cause a change at its output. Most circuit families define delays in terms of minimum (best case), typical (average), and maximum (worst case) times. A corollary to Murphy's law, well known to experienced digital designers, is that if a circuit can run at its worst-case delay, it will. Never assume that your design will be able to run with minimum delay.

What would happen if you depended on a portion of your design running with minimum delay? If its delay is longer than you designed for, you may examine its output too soon, incorrectly computing the final output of your overall system.

The various families of TTL exhibit trade-offs between delay and power. The faster a component, the more power it consumes. Table 3.1 shows some timing information for typical TTL gates. Did you notice that propagation delays often depend on whether the output is going from low to high, written as tpLH, or from high to low, tpHL?

For two-input NAND gates, 74X00, the lower-power TTL families (L, LS), are substantially slower than higher-speed logic (H, S). Two-input NOR gates, 74X02, exhibit comparable delays. For a given TTL family, such as LS, more complex components tend to be slower. This is shown in Table 3.1 for the 74LS86A two-input XOR gate.

3.3.2 Timing Waveforms

Let's consider the circuit shown in Figure 3.26.

An input signal A passes through three inversions, leaving it in its inverted state, which is then ANDed with the original input. This appears to implement a rather useless function: . However, the timing diagram of Figure 3.27 tells us a different story. After the input A goes high, the output waveform goes high for a short time before going low. Such a circuit is called a pulse shaper because a change at its input causes a short-duration pulse at the output.

The circuit of Figure 3.26 operates as follows. Let's assume that the initial state has A = 0, B = 1, C = 0, D = 1, and F = 0, as shown in Figure 3.27 at time step 0.

Further, we assume that each gate has a propagation delay of 10 time units. When input A changes from 0 to 1 at time 10, it takes 10 time units, a gate delay, before B changes from 1 to 0 (time step 20). After a second gate delay, C changes from 0 to 1 (time step 30). D changes from 1 to 0 after a third gate delay (time step 40). However, between time 10 and time 40, both A and D are logic 1. If the AND gate also has a 10-unit gate delay, the output F will be high between time steps 20 and 50. This is exactly what is shown in the timing diagram. In effect, the three inverters stretch the time during which A and D are both logic 1 after A changes from 0 to 1. Eventually, the change in A propagates to D as a 0, causing F to fall after another gate delay. It is no surprise that the pulse is exactly three inverter delays wide. If we increased the number of inverters to five, the width of the pulse would be five gate delays instead.

A pulse shaper circuit exploits the propagation asymmetries in signal paths with the explicit purpose of creating short-duration changes at the output. It generates a periodic waveform that could be used, for example, as a clock in a digital system. It operates much like a stopwatch. With its switch in one position, the circuit does nothing. In the second position, the circuit generates a periodic sequence of pulses.

Analysis of a Pulse Shaper Circuit

In this section, we will analyze the operation of the simple pulse shaper circuit of Figure 3.28.

The circuit has a single input A that is connected to a logic 1 when the switch is open and to a logic 0 when the switch is closed. This is because the path to ground has lower resistance than the path to the power supply when the switch is closed (switches are discussed in more detail in Section 3.5.3). We will assume that the propagation delay of all gates is 10 time units.

Let's suppose that at time step 0, the switch has just been closed. We begin by determining the initial value for each of the circuit's nets. A goes to 0 instantly. Since a NAND gate will output a 1 whenever one of its inputs is 0, B goes to 1, but after a gate delay of 10 time units. So we say that B goes to 1 at time step 10.

C is set to the complement of B, but once again only after an inverter propagation delay. Thus C goes to 0 at time step 20. D becomes the complement of C after another inverter delay. So it goes to 1 at time step 30. Since A is 0 and D is 1, the output of the NAND gate stays at 0. The circuit is said to be in a steady state.

What happens if the switch opens at time step 40? The input A immediately goes to 1. Now both inputs to the NAND gate are 1, so after a gate propagation of 10 time units, B will go low. This happens at time step 50.

The change in B propagates to C after another inverter delay. Thus at time step 60, C goes to 1. In a similar fashion, D goes to 0 at time step 70. Now the NAND gate has one of its inputs at 0, so at time step 80 B will go to 1.

Note that B first goes low at time step 50 and goes high at time step 80-a difference of 30 time units. This is exactly three gate delays: the delay through the NAND gate and the two inverter gates on the path from signal B to D.

Now that B is at 1, C will go to 0 at time step 90, D will go to 1 at time step 100, and B will return to 0 at time step 110. The circuit is no longer in steady state. It now oscillates with B, C, and D varying between 1 and 0, staying at each value for three gate delays (30 time units). The behavior of the circuit is summarized in the timing diagram of Figure 3.29.

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This file last updated on 07/07/96 at 18:44:30.
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