List of Tables

Chapter 1: The Campus Network

Figure 1.1: A traditional 80/20 network

Figure 1.2: A 20/80 network

Figure 1.3: VLANs break up broadcast domains in a switched internetwork.

Figure 1.4: The OSI model and the layer functions

Figure 1.5: Data encapsulation at each layer of the OSI reference model

Figure 1.6: The Cisco hierarchical model

Figure 1.7: A hierarchical network design

Figure 1.8: The core block

Figure 1.9: Collapsed core

Figure 1.10: Dual-core configuration

Figure 1.11: Layer 2 backbone scaling without STP

Figure 1.12: Enterprise Composite Module

Figure 1.13: Enterprise SAFE block diagram

Figure 1.14: Enterprise Campus Module detailed diagram

Chapter 2: Connecting the Switch Block

Figure 2.1: Access layer to distribution layer configuration

Chapter 3: VLANs, Trunks, and VTP

Figure 3.1: A flat network structure

Figure 3.2: Switches remove the physical boundary.

Figure 3.3: Physical LANs connected to a router

Figure 3.4: VTP modes

Figure 3.5: VTP advertisement content

Figure 3.6: Subset advertisement

Figure 3.7: VTP revision number

Figure 3.8: VTP pruning

Figure 3.9: Switched internetwork for hands-on lab

Chapter 4: Layer 2 Switching and the Spanning Tree Protocol (STP)

Figure 4.1: How switches learn hosts' locations

Figure 4.2: Broadcast storms

Figure 4.3: Multiple frame copies

Figure 4.4: Spanning tree operations

Figure 4.5: STP default timers

Figure 4.6: Spanning tree example

Figure 4.7: Different switching modes within a frame

Chapter 5: Using Spanning Tree with VLANs

Figure 5.1: Prioritizing traffic by VLAN

Figure 5.2: Network diagram for the hands-on lab

Chapter 6: Inter-VLAN Routing

Figure 6.1: Routers with multiple links

Figure 6.2: Single trunk link for all VLANs

Figure 6.3: Configuring inter-VLAN communication for the hands-on labs

Chapter 7: Multilayer Switching (MLS)

Figure 7.1: Router-on-a-stick diagram

Figure 7.2: MLS example topology

Figure 7.3: MLSP discovery

Figure 7.4: Candidate packet

Figure 7.5: Enable packet

Figure 7.6: Frame modification

Figure 7.7: Router on a stick

Figure 7.8: Multiple switches, one router

Figure 7.9: Process switching flow

Figure 7.10: Fast switching tree

Figure 7.11: Optimum switching tree

Figure 7.12: CEF forwarding process

Figure 7.13: Lab topology

Chapter 8: Understanding and Configuring Multicast Operation

Figure 8.1: Unicast communication

Figure 8.2: Broadcast message on a network

Figure 8.3: Multicast communication

Figure 8.4: IP multicast mapped to MAC multicast

Figure 8.5: Example 1 for mapping IP multicast to MAC multicast addresses

Figure 8.6: Example 2 for mapping IP multicast to MAC multicast addresses

Figure 8.7: Multicast addressing overlap

Figure 8.8: IGMPv1 Query routine

Figure 8.9: Unsolicited join requests

Figure 8.10: IGMPv2 Leave process

Figure 8.11: CGMP Join process

Figure 8.12: Source tree forwarding

Figure 8.13: Shared tree forwarding

Figure 8.14: Bidirectional shared tree

Figure 8.15: TTL threshold utilization

Figure 8.16: DVMRP tunnels

Figure 8.17: PIM DM flooding

Figure 8.18: PIM DM pruning

Figure 8.19: PIM DM grafting

Figure 8.20: CBT data distribution

Figure 8.21: PIM SM pruning

Figure 8.22: Configuring an IP multicast network

Chapter 9: Quality of Service (QoS)

Figure 9.1: E-mail application fragments

Figure 9.2: HTTP application fragments

Figure 9.3: Voice playback buffers

Figure 9.4: Voice design model

Figure 9.5: Best efforts packets

Figure 9.6: Differentiated Services model

Figure 9.7: Basic QoS model

Figure 9.8: Frame and packet marking

Figure 9.9: Queuing overview

Figure 9.10: HSRP virtual router

Figure 9.11: HSRP hello process

Figure 9.12: Network diagram for the hands-on lab

Chapter 10: Catalyst Switch Technologies

Figure 10.1: Non-blocking switch fabric

Figure 10.2: Bus switching fabric

Figure 10.3: Shared memory switching fabric

Figure 10.4: Crossbar switching fabric

Figure 10.5: Contiguous buffering

Figure 10.6: Particle buffers

Figure 10.7: 2950 switch architecture

Figure 10.8: 3550 switch architecture

Figure 10.9: 4000 switch architecture

Figure 10.10: 6500 switch architecture