6.6 Floating Point Arithmetic

6.6 Floating Point Arithmetic

When the 8086 CPU first appeared in the late 1970s, semiconductor technology was not to the point where Intel could put floating point instructions directly on the 8086 CPU. Therefore, it devised a scheme whereby it could use a second chip to perform the floating point calculations — the floating point unit (or FPU).^[2] It released its original floating point chip, the 8087, in 1980. This particular FPU worked with the 8086, 8088, 80186, and 80188 CPUs. When Intel introduced the 80286 CPU, it released a redesigned 80287 FPU chip to accompany it. Although the 80287 was compatible with the 80386 CPU, Intel designed a better FPU, the 80387, for use in 80386 systems. The 80486 CPU was the first Intel CPU to include an on-chip floating point unit. Shortly after the release of the 80486, Intel introduced the 80486sx CPU that was an 80486 without the built-in FPU. To get floating point capabilities on this chip, you had to add an 80487 chip, although the 80487 was really nothing more than a full-blown 80486 that took over for the "sx" chip in the system. Intel's Pentium chips provide a highperformance floating point unit directly on the CPU. There is no (Intel) floating point coprocessor available for the Pentium chip.

Collectively, we will refer to all these chips as the 80x87 FPU. Given the obsolescence of the 8086, 80286, 8087, 80287, 80387, and 80487 chips, this text will concentrate on the Pentium and later chips. There are some differences between the Pentium floating point units and the earlier FPUs. If you need to write code that will execute on those earlier machines, you should consult the appropriate Intel documentation for those devices.

6.6.1 FPU Registers

The 80x86 FPUs add 13 registers to the 80x86 and later processors: 8 floating point data registers, a control register, a status register, a tag register, an instruction pointer, and a data pointer. The data registers are similar to the 80x86's general purpose register set insofar as all floating point calculations take place in these registers. The control register contains bits that let you decide how the FPU handles certain degenerate cases like rounding of inaccurate computations, it contains bits that control precision, and so on. The status register is similar to the 80x86's flags register; it contains the condition code bits and several other floating point flags that describe the state of the FPU. The tag register contains several groups of bits that determine the state of the value in each of the eight general purpose registers. The instruction and data pointer registers contain certain state information about the last floating point instruction executed. We will not consider the last three registers in this text; see the Intel documentation for more details.

6.6.1.1 FPU Data Registers

The FPUs provide eight 80-bit data registers organized as a stack. This is a significant departure from the organization of the general purpose registers on the 80x86 CPU that comprise a standard general purpose register set. HLA refers to these registers as ST0, ST1, …, ST7.

The biggest difference between the FPU register set and the 80x86 register set is the stack organization. On the 80x86 CPU, the AX register is always the AX register, no matter what happens. On the FPU, however, the register set is an eight-element stack of 80-bit floating point values (see Figure 6-1).

Figure 6-1: FPU Floating Point Register Stack.

ST0 refers to the item on the top of the stack, ST1 refers to the next item on the stack, and so on. Many floating point instructions push and pop items on the stack; therefore, ST1 will refer to the previous contents of ST0 after you push something onto the stack. It will take some thought and practice to get used to the fact that the registers are changing, but this is an easy problem to overcome.

6.6.1.2 The FPU Control Register

When Intel designed the 80x87 (and, essentially, the IEEE floating point standard), there were no standards in floating point hardware. Different (mainframe and mini) computer manufacturers all had different and incompatible floating point formats. Unfortunately, much application software had been written taking into account the idiosyncrasies of these different floating point formats. Intel wanted to design an FPU that could work with the majority of the software out there (keep in mind, the IBM PC was three to four years away when Intel began designing the 8087; it couldn't rely on that "mountain" of software available for the PC to make its chip popular). Unfortunately, many of the features found in these older floating point formats were mutually incompatible. For example, in some floating point systems rounding would occur when there was insufficient precision; in others, truncation would occur. Some applications would work with one floating point system but not with another. Intel wanted as many applications as possible to work with as few changes as possible on its 80x87 FPUs, so it added a special register, the FPU control register, that lets the user choose one of several possible operating modes for their FPU.

The 80x87 control register contains 16-bits organized as shown in Figure 6-2.

Figure 6-2: FPU Control Register.

Bits 10 and 11 of the FPU control register provide rounding control according to the values appearing in Table 6-8.

Table 6-8: Rounding Control

Bits 10 & 11	Function
00	To nearest or even
01	Round down
10	Round up
11	Truncate

The "00" setting is the default. The FPU rounds values above one-half of the least significant bit up. It rounds values below one-half of the least significant bit down. If the value below the least significant bit is exactly one-half of the least significant bit, the FPU rounds the value toward the value whose least significant bit is zero. For long strings of computations, this provides a reasonable, automatic way to maintain maximum precision.

The round up and round down options are present for those computations where it is important to keep track of the accuracy during a computation. By setting the rounding control to round down and performing the operation, then repeating the operation with the rounding control set to round up, you can determine the minimum and maximum ranges between which the true result will fall.

The truncate option forces all computations to truncate any excess bits during the computation. You will rarely use this option if accuracy is important to you. However, if you are porting older software to the FPU, you might use this option to help when porting the software. One place where this option is extremely useful is when converting a floating point value to an integer. Because most software expects floating point-to-integer conversions to truncate the result, you will need to use the truncation rounding mode to achieve this.

Bits eight and nine of the control register specify the precision during computation. This capability is provided to allow compatibility with older software as required by the IEEE 754 standard. The precision control bits use the values in Table 6-9.

Table 6-9: Mantissa Precision Control Bits

Bits 8 & 9	Precision Control
00	24 bits
01	Reserved
10	53 bits
11	64 bits

Some CPUs may operate faster with floating point values whose precision is 53 bits (i.e., 64-bit floating point format) rather than 64 bits (i.e., 80-bit floating point format). Please see the documentation for your specific processor for details. Generally, the CPU defaults these bits to %11 to select the 64-bit mantissa precision.

Bits zero through five are the exception masks. These are similar to the interrupt enable bit in the 80x86's flags register. If these bits contain a one, the corresponding condition is ignored by the FPU. However, if any bit contains zero, and the corresponding condition occurs, then the FPU immediately generates an interrupt so the program can handle the degenerate condition (typically, this would wind up raising in HLA exception; see the excepts.hhf header file for the exception values).

Bit zero corresponds to an invalid operation error. This generally occurs as the result of a programming error. Problems that raise the invalid operation exception include pushing more than eight items onto the stack or attempting to pop an item off an empty stack, taking the square root of a negative number, or loading a non-empty register.

Bit one masks the denormalized interrupt that occurs whenever you try to manipulate denormalized values. Denormalized exceptions occur when you load arbitrary extended precision values into the FPU or work with very small numbers just beyond the range of the FPU's capabilities. Normally, you would probably not enable this exception. If you enable this exception and the FPU generates this interrupt, the HLA run-time system raises the ex.fDenormal exception.

Bit two masks the zero divide exception. If this bit contains zero, the FPU will generate an interrupt if you attempt to divide a non-zero value by zero. If you do not enable the zero division exception, the FPU will produce NaN (not a number) whenever you perform a zero division. It's probably a good idea to enable this exception by programming a zero into this bit. Note that if your program generates this interrupt, the HLA run-time system will raise the ex.fDivByZero exception.

Bit three masks the overflow exception. The FPU will raise the overflow exception if a calculation overflows or if you attempt to store a value that is too large to fit into the destination operand (e.g., storing a large extended precision value into a single precision variable). If you enable this exception and the FPU generates this interrupt, the HLA run-time system raises the ex.fOverflow exception.

Bit four, if set, masks the underflow exception. Underflow occurs when the result is too small to fit in the destination operand. Like overflow, this exception can occur whenever you store a small extended precision value into a smaller variable (single or double precision) or when the result of a computation is too small for extended precision. If you enable this exception and the FPU generates this interrupt, the HLA run-time system raises the ex.fUnderflow exception.

Bit five controls whether the precision exception can occur. A precision exception occurs whenever the FPU produces an imprecise result, generally the result of an internal rounding operation. Although many operations will produce an exact result, many more will not. For example, dividing one by ten will produce an inexact result. Therefore, this bit is usually one because inexact results are very common. If you enable this exception and the FPU generates this interrupt, the HLA run-time system raises the ex.InexactResult exception.

Bits six and thirteen through fifteen in the control register are currently undefined and reserved for future use. Bit seven is the interrupt enable mask, but it is only active on the 80x87 FPU; a zero in this bit enables 80x87 interrupts and a one disables FPU interrupts.

The FPU provides two instructions, fldcw (load control word) and fstcw(store control word), that let you load and store the contents of the control register. The single operand to these instructions must be a 16-bit memory location. The fldcw instruction loads the control register from the specified memory location, fstcw stores the control register into the specified memory location. The syntax for these instructions is

 fldcw( mem16 ); fstcw( mem16 ); 

Here's some example code that sets the rounding control to "truncate result" and sets the rounding precision to 24 bits:

 static      fcw16: word;           .           .           .      fstcw( fcw16 );      mov( fcw16, ax );      and( $f0ff, ax );     // Clears bits 8-11.      or( $0c00, ax );      // Rounding control=%11, Precision = %00.      mov( ax, fcw16 );      fldcw( fcw16 ); 

6.6.1.3 The FPU Status Register

The FPU status register provides the status of the coprocessor at the instant you read it. The FSTSW instruction stores the16-bit floating point status register into a word variable. The status register is a 16-bit register; its layout appears in Figure 6-3.

Figure 6-3: The FPU Status Register.

Bits zero through five are the exception flags. These bits are appear in the same order as the exception masks in the control register. If the corresponding condition exists, then the bit is set. These bits are independent of the exception masks in the control register. The FPU sets and clears these bits regardless of the corresponding mask setting.

Bit six indicates a stack fault. A stack fault occurs whenever there is a stack overflow or underflow. When this bit is set, the C₁ condition code bit determines whether there was a stack overflow (C₁=1) or stack underflow (C₁=0) condition.

Bit seven of the status register is set if any error condition bit is set. It is the logical OR of bits zero through five. A program can test this bit to quickly determine if an error condition exists.

Bits 8, 9, 10, and 14 are the coprocessor condition code bits. Various instructions set the condition code bits, as shown in Tables 6-10 and 6-11, respectively.

Table 6-10: FPU Condition Code Bits

Instruction	Condition Code Bits				Condition
	C3	C2	C1	C0
fcom,	0	0	X	0	ST>source
fcomp,	0	0	X	1	ST<source
fcompp,	1	0	X	0	ST=source
ficom, ficomp	1	1	X	1	ST or source undefined
ftst	0	0	X	0	ST is positive
	0	0	X	1	ST is negative
	1	0	X	0	ST is zero (+ or −)
	1	1	X	1	ST is uncomparable
fxam	0	0	0		+ Unnormalized
	0	0	1	0	−Unnormalized
	0	1	0	0	+Normalized
	0	1	1	0	−Normalized
	1	0	0	0	+0
	1	0	1	0	−0
	1	1	0	0	+Denormalized
	1	1	1	0	−Denormalized
	0	0	0	1	+NaN
	0	0	1	1	−NaN
	0	1	0	1	+Infinity
	0	1	1	1	−Infinity
	1	X	X	1	Empty register
fucom	0	0	X	0	ST > source
fucomp,	0	0	X	1	ST < source
fucompp,	1	0	X	0	ST = source
	1	1	X	1	Unordered
					X=Don't care

Table 6-11: Condition Code Interpretations

Instructions	Condition Code Bits
	C0	C3	C2	C1
fcom, fcomp, fcmpp, ftst, fucom, fucomp, fucompp, ficom, ficomp	Result of comparison. See previous table.	Result of comparison. See previous table.	Operands are not comparable.	Result of comparison. See previous table. Also denotes stack overflow/underflow if stack exception bit is set.
fxam	See previous table.	See previous table.	See previous table.	Sign of result, or stack overflow/underflow (if stack exception bit is set).
fprem, fprem1	Bit 2 of remainder	Bit 0 of remainder	0- reduction done. 1- reduction incomplete.	Bit 1 of remainder of stack overflow/underflow (if stack exception bit is set).
fist, fbstp, frndint, fst, fstp, fadd, fmul, fdiv, fdivr, fsub, fsubr, fscale, fsqrt, fpatan, f2xm1, fyl2x, fyl2xp1	Undefined	Undefined	Undefined	Round up occurred or stack overflow/underflow (if stack exception bit is set).
fptan, fsin, fcos, fsincos	Undefined	Undefined	0- reduction done. 1- reduction incomplete.	Round up occurred or stack overflow/underflow (if stack exception bit is set).
fchs, fabs, fxch, fincstp, fdecstp, constant loads, fxtract, fld, fild, fbld, fstp (80 bit)	Undefined	Undefined	Undefined	Zero result or stack overflow/underflow (if stack exception bit is set).
fldenv, fstor	Restored from memory operand.	Restored from memory operand.	Restored from memory operand.	Restored from memory operand.
fldcw, fstenv, fstcw, fstsw, fclex	Undefined	Undefined	Undefined	Undefined
finit, fsave	Cleared to zero.	Cleared to zero.	Cleared to zero.	Cleared to zero.

Bits 11-13 of the FPU status register provide the register number of the top of stack. During computations, the FPU adds (modulo 8) the logical register numbers supplied by the programmer to these three bits to determine the physical register number at runtime.

Bit 15 of the status register is the busy bit. It is set whenever the FPU is busy. Most programs will have little reason to access this bit.

6.6.2 FPU Data Types

The FPU supports seven different data types: three integer types, a packed decimal type, and three floating point types. The integer type provides for 64-bit integers, although it is often faster to do the 64-bit arithmetic using the integer unit of the CPU (see the chapter on advanced arithmetic). Certainly it is faster to do 16-bit and 32-bit integer arithmetic using the standard integer registers. The packed decimal type provides a 17-digit signed decimal (BCD) integer. The primary purpose of the BCD format is to convert between strings and floating point values. The remaining three data types are the 32-bit, 64-bit, and 80-bit floating point data types we've looked at so far. The 80x87 data types appear in Figures 6-4, 6-5, and 6-6.

Figure 6-4: FPU Floating Point Formats.

Figure 6-5: FPU Integer Formats.

Figure 6-6: FPU Packed Decimal Format.

The FPU generally stores values in a normalized format. When a floating point number is normalized, the H.O. bit of the mantissa is always one. In the 32- and 64-bit floating point formats, the FPU does not actually store this bit, the FPU always assumes that it is one. Therefore, 32- and 64-bit floating point numbers are always normalized. In the extended precision 80-bit floating point format, the FPU does not assume that the H.O. bit of the mantissa is one; the H.O. bit of the mantissa appears as part of the string of bits.

Normalized values provide the greatest precision for a given number of bits. However, there is a large number of non-normalized values that we cannot represent with the 80-bit format. These values are very close to zero and represent the set of values whose mantissa H.O. bit is not zero. The FPUs support a special 80-bit form known as denormalized values. Denormalized values allow the FPU to encode very small values it cannot encode using normalized values, but at a price. Denormalized values offer fewer bits of precision than normalized values. Therefore, using denormalized values in a computation may introduce some slight inaccuracy into a computation. Of course, this is always better than underflowing the denormalized value to zero (which could make the computation even less accurate), but you must keep in mind that if you work with very small values you may lose some accuracy in your computations. Note that the FPU status register contains a bit you can use to detect when the FPU uses a denormalized value in a computation.

6.6.3 The FPU Instruction Set

The FPU adds over 80 new instructions to the 80x86 instruction set. We can classify these instructions as data movement instructions, conversions, arithmetic instructions, comparisons, constant instructions, transcendental instructions, and miscellaneous instructions. The following sections describe each of the instructions in these categories.

6.6.4 FPU Data Movement Instructions

The data movement instructions transfer data between the internal FPU registers and memory. The instructions in this category are fld, fst, fstp, and fxch. The fld instruction always pushes its operand onto the floating point stack. The fstp instruction always pops the top of stack after storing the top of stack. The remaining instructions do not affect the number of items on the stack.

6.6.4.1 The FLD Instruction

The fld instruction loads a 32-bit, 64-bit, or 80-bit floating point value onto the stack. This instruction converts 32- and 64-bit operands to an 80-bit extended precision value before pushing the value onto the floating point stack.

The fld instruction first decrements the top of stack (TOS) pointer (bits 11 through 13 of the status register) and then stores the 80-bit value in the physical register specified by the new TOS pointer. If the source operand of the FLD instruction is a floating point data register, STi, then the actual register the FPU uses for the load operation is the register number before decrementing the TOS pointer. Therefore, "fld( st0 );" duplicates the value on the top of the stack.

The fld instruction sets the stack fault bit if stack overflow occurs. It sets the denormalized exception bit if you load an 80-bit denormalized value. It sets the invalid operation bit if you attempt to load an empty floating point register onto the top of stack (or perform some other invalid operation). Examples:

      fld( st1 );      fld( real32_variable );      fld( real64_variable );      fld( real80_variable );      fld( (type real64 [ebx]) );      fld( real_constant ); 

Note that there is no way to directly load a 32-bit integer register onto the floating point stack, even if that register contains a real32 value. To accomplish this, you must first store the integer register into a memory location then you can push that memory location onto the FPU stack using the fld instruction. E.g.,

      mov( eax, tempReal32 );      // Save REAL32 value in EAX to memory.      fld( tempReal32 );           // Push that real value onto the FPU stack. 

Note

Loading a constant via fld is actually an HLA extension. The FPU doesn't support this instruction type. HLA creates a real80 object in the constants segment and uses the address of this memory object as the true operand for fld.

6.6.4.2 The FST and FSTP Instructions

The fst and fstp instructions copy the value on the top of the floating point register stack to another floating point register or to a 32-, 64-, or 80-bit memory variable. When copying data to a 32- or 64-bit memory variable, the 80-bit extended precision value on the top of stack is rounded to the smaller format as specified by the rounding control bits in the FPU control register.

The fstp instruction pops the value off the top of stack when moving it to the destination location. It does this by incrementing the top of stack pointer in the status register after accessing the data in ST0. If the destination operand is a floating point register, the FPU stores the value at the specified register number before popping the data off the top of the stack.

Executing an "fstp( st0 );" instruction effectively pops the data off the top of stack with no data transfer. Examples:

      fst( real32_variable );      fst( real64_variable );      fst( realArray[ ebx*8 ] );      fst( real80_variable );      fst( st2 );      fstp( st1 ); 

The last example preceding effectively pops ST1 while leaving ST0 on the top of the stack.

The fst and fstp instructions will set the stack exception bit if a stack underflow occurs (attempting to store a value from an empty register stack). They will set the precision bit if there is a loss of precision during the store operation (this will occur, for example, when storing an 80-bit extended precision value into a 32- or 64-bit memory variable and there are some bits lost during conversion). They will set the underflow exception bit when storing an 80-bit value into a 32- or 64-bit memory variable, but the value is too small to fit into the destination operand. Likewise, these instructions will set the overflow exception bit if the value on the top of stack is too big to fit into a 32- or 64-bit memory variable. The fst and fstp instructions set the denormalized flag when you try to store a denormalized value into an 80-bit register or variable.^[3] They set the invalid operation flag if an invalid operation (such as storing into an empty register) occurs. Finally, these instructions set the C1 condition bit if rounding occurs during the store operation (this only occurs when storing into a 32- or 64-bit memory variable and you have to round the mantissa to fit into the destination).

Note

Because of an idiosyncrasy in the FPU instruction set related to the encoding of the instructions, you cannot use the fst instruction to store data into a real80 memory variable. You may, however, store 80-bit data using the fstp instruction.

6.6.4.3 The FXCH Instruction

The fxch instruction exchanges the value on the top of stack with one of the other FPU registers. This instruction takes two forms: one with a single FPU register as an operand, the second without any operands. The first form exchanges the top of stack (TOS) with the specified register. The second form of fxch swaps the top of stack with ST1.

Many FPU instructions, e.g., fsqrt, operate only on the top of the register stack. If you want to perform such an operation on a value that is not on the top of stack, you can use the fxch instruction to swap that register with TOS, perform the desired operation, and then use the fxch to swap the TOS with the original register. The following example takes the square root of ST2:

      fxch( st2 );      fsqrt();      fxch( st2 ); 

The fxch instruction sets the stack exception bit if the stack is empty. It sets the invalid operation bit if you specify an empty register as the operand. This instruction always clears the C₁ condition code bit.

6.6.5 Conversions

The FPU performs all arithmetic operations on 80 bit real quantities. In a sense, the fld and fst/fstp instructions are conversion instructions because they automatically convert between the internal 80-bit real format and the 32- and 64-bit memory formats. Nonetheless, we'll simply classify them as data movement operations, rather than conversions, because they are moving real values to and from memory. The FPU provides five other instructions that convert to or from integer or binary coded decimal (BCD) format when moving data. These instructions are fild, fist, fistp, fbld, and fbstp.

6.6.5.1 The FILD Instruction

The fild (integer load) instruction converts a 16-, 32-, or 64-bit two's complement integer to the 80-bit extended precision format and pushes the result onto the stack. This instruction always expects a single operand. This operand must be the address of a word, double word, or quad word integer variable. You cannot specify one of the 80x86's 16- or 32-bit general purpose registers. If you want to push an 80x86 general purpose register onto the FPU stack, you must first store it into a memory variable and then use fild to push that value of that memory variable.

The fild instruction sets the stack exception bit and C₁ (accordingly) if stack overflow occurs while pushing the converted value. Examples:

      fild( word_variable );      fild( dword_val[ ecx*4 ] );      fild( qword_variable );      fild( (type int64 [ebx]) ); 

6.6.5.2 The FIST and FISTP Instructions

The fist and fistp instructions convert the 80-bit extended precision variable on the top of stack to a 16-, 32-, or 64-bit integer and store the result away into the memory variable specified by the single operand. These instructions convert the value on TOS to an integer according to the rounding setting in the FPU control register (bits 10 and 11). As for the fild instruction, the fist and fistp instructions will not let you specify one of the 80x86's general purpose 16- or 32-bit registers as the destination operand.

The fist instruction converts the value on the top of stack to an integer and then stores the result; it does not otherwise affect the floating point register stack. The fistp instruction pops the value off the floating point register stack after storing the converted value.

These instructions set the stack exception bit if the floating point register stack is empty (this will also clear C₁). They set the precision (imprecise operation) and C₁ bits if rounding occurs (that is, if there is any fractional component to the value in ST0). These instructions set the underflow exception bit if the result is too small (i.e., less than one but greater than zero or less than zero but greater than -1). Examples:

      fist( word_var[ ebx*2 ] );      fist( qword_var );      fistp( dword_var ); 

Don't forget that these instructions use the rounding control settings to determine how they will convert the floating point data to an integer during the store operation. Be default, the rounding control is usually set to "round" mode; yet most programmers expect fist/fistp to truncate the decimal portion during conversion. If you want fist/fistp to truncate floating point values when converting them to an integer, you will need to set the rounding control bits appropriately in the floating point control register, e.g.,

 static      fcw16:           word;      fcw16_2:         word;      IntResult:       int32;           .           .           .           fstcw( fcw16 );           mov( fcw16, ax );           or( $0c00, ax );      // Rounding control=%11 (truncate).           mov( ax, fcw16_2 );   // Store into memory and reload the ctrl word.           fldcw( fcw16_2 );           fistp( IntResult );   // Truncate ST0 and store as int32 object.           fldcw( fcw16 );       // Restore original rounding control 

6.6.5.3 The FBLD and FBSTP Instructions

The fbld and fbstp instructions load and store 80-bit BCD values. The fbld instruction converts a BCD value to its 80-bit extended precision equivalent and pushes the result onto the stack. The fbstp instruction pops the extended precision real value on TOS, converts it to an 80 bit BCD value (rounding according to the bits in the floating point control register), and stores the converted result at the address specified by the destination memory operand. Note that there is no fbst instruction.

The fbld instruction sets the stack exception bit and C₁ if stack overflow occurs. It sets the invalid operation bit if you attempt to load an invalid BCD value. The fbstp instruction sets the stack exception bit and clears C₁ if stack underflow occurs (the stack is empty). It sets the underflow flag under the same conditions as fist and fistp. Examples:

 // Assuming fewer than 8 items on the stack, the following // code sequence is equivalent to an fbst instruction:           fld( st0 );           fbstp( tbyte_var ); // The following example easily converts an 80-bit BCD value to // a 64-bit integer:           fbld( tbyte_var );           fist( qword_var ); 

These two instructions are especially useful for converting between string and floating point formats. See the conversion routines in the HLA Standard Library for more details.

6.6.6 Arithmetic Instructions

The arithmetic instructions make up a small, but important, subset of the FPU's instruction set. These instructions fall into two general categories — those that operate on real values and those that operate on a real and an integer value.

6.6.6.1 The FADD and FADDP Instructions

These two instructions take the following forms:

      fadd()      faddp()      fadd( st0, sti );      fadd( sti, st0 );      faddp( st0, sti );      fadd( mem_32_64 );      fadd( real_constant ); 

The first two forms are equivalent. They pop the two values on the top of stack, add them, and push their sum back onto the stack.

The next two forms of the fadd instruction, those with two FPU register operands, behave like the 80x86's add instruction. They add the value in the source register operand to the value in the destination register operand. Note that one of the register operands must be ST0.

The faddp instruction with two operands adds ST0 (which must always be the source operand) to the destination operand and then pops ST0. The destination operand must be one of the other FPU registers.

The last form above, fadd with a memory operand, adds a 32- or 64-bit floating point variable to the value in ST0. This instruction will convert the 32- or 64-bit operands to an 80-bit extended precision value before performing the addition. Note that this instruction does not allow an 80-bit memory operand.

These instructions can raise the stack, precision, underflow, overflow, denormalized, and illegal operation exceptions, as appropriate. If a stack fault exception occurs, C₁ denotes stack overflow or underflow.

Like fld( real_constant ), the fadd( real_constant ) instruction is an HLA extension. Note that it creates a 64-bit variable holding the constant value and emits the fadd( mem64 ) instruction, specifying the read-only object it creates in the constants segment.

6.6.6.2 The FSUB, FSUBP, FSUBR, and FSUBRP Instructions

These four instructions take the following forms:

      fsub()      fsubp()      fsubr()      fsubrp()      fsub( st0, sti )      fsub( sti, st0 );      fsubp( st0, sti );      fsub( mem_32_64 );      fsub( real_constant );      fsubr( st0, sti )      fsubr( sti, st0 );      fsubrp( st0, sti );      fsubr( mem_32_64 );      fsubr( real_constant ); 

With no operands, the fsub and fsubp instructions operate identically. They pop ST0 and ST1 from the register stack, compute ST1-ST0, and then push the difference back onto the stack. The fsubr and fsub rp instructions (reverse subtraction) operate in an almost identical fashion, except they compute ST0-ST1 and push that difference.

With two register operands ( source, destination ) the fsub instruction computes destination := destination - source. One of the two registers must be ST0. With two registers as operands, the fsubp also computes destination := destination - source and then it pops ST0 off the stack after computing the difference. For the fsubp instruction, the source operand must be ST0.

With two register operands, the fsubr and fsubrp instruction work in a similar fashion to fsub and fsubp, except they compute destination := source - destination.

The fsub(mem) and fsubr(mem) instructions accept a 32- or 64-bit memory operand. They convert the memory operand to an 80-bit extended precision value and subtract this from ST0 (fsub) or subtract ST0 from this value (fsubr) and store the result back into ST0.

These instructions can raise the stack, precision, underflow, overflow, denormalized, and illegal operation exceptions, as appropriate. If a stack fault exception occurs, C₁ denotes stack overflow or underflow.

Note: the instructions that have real constants as operands aren't true FPU instructions. These are extensions provided by HLA. HLA generates a read-only memory object initialized with the constant's value.

6.6.6.3 The FMUL and FMULP Instructions

The fmul and fmulp instructions multiply two floating point values. These instructions allow the following forms:

      fmul()      fmulp()      fmul( sti, st0 );      fmul( st0, sti );      fmul( mem_32_64 );      fmul( real_constant );      fmulp( st0, sti ); 

With no operands, fmul and fmulp both do the same thing: They pop ST0 and ST1, multiply these values, and push their product back onto the stack. The fmul instructions with two register operands compute destination := destination * source. One of the registers (source or destination) must be ST0.

The fmulp( ST0, STi ) instruction computes STi := STi * ST0 and then pops ST0. This instruction uses the value for i before popping ST0. The fmul(mem) instruction requires a 32- or 64-bit memory operand. It converts the specified memory variable to an 80-bit extended precision value and then multiplies ST0 by this value.

These instructions can raise the stack, precision, underflow, overflow, denormalized, and illegal operation exceptions, as appropriate. If rounding occurs during the computation, these instructions set the C₁ condition code bit. If a stack fault exception occurs, C₁ denotes stack overflow or underflow.

Note

The instruction that has a real constant as its operand isn't a true FPU instruction. It is an extension provided by HLA (see the note at the end of the previous section for details).

6.6.6.4 The FDIV, FDIVP, FDIVR, and FDIVRP Instructions

These four instructions allow the following forms:

      fdiv()      fdivp()      fdivr()      fdivrp()      fdiv( sti, st0 );      fdiv( st0, sti );      fdivp( st0, sti );      fdivr( sti, st0 );      fdivr( st0, sti );      fdivrp( st0, sti );      fdiv( mem_32_64 );      fdivr( mem_32_64 );      fdiv( real_constant );      fdivr( real_constant ); 

With no operands, the fdiv and fdivp instructions pop ST0 and ST1, compute ST1/ST0, and push the result back onto the stack. The fdivr and fdivrp instructions also pop ST0 and ST1 but compute ST0/ST1 before pushing the quotient onto the stack.

With two register operands, these instructions compute the following quotients:

      fdiv( sti, st0 );      // ST0 := ST0/STi      fdiv( st0, sti );      // STi := STi/ST0      fdivp( st0, sti );     // STi := STi/ST0 then pop ST0      fdivr( st0, sti );     // ST0 := ST0/STi      fdivrp( st0, sti );    // STi := ST0/STi then pop ST0 

The fdivp and fdivrp instructions also pop ST0 after performing the division operation. The value for i in these two instructions is computed before popping ST0.

These instructions can raise the stack, precision, underflow, overflow, denormalized, zero divide, and illegal operation exceptions, as appropriate. If rounding occurs during the computation, these instructions set the C₁ condition code bit. If a stack fault exception occurs, C₁ denotes stack overflow or underflow.

Note

The instructions that have real constants as operands aren't true FPU instructions. These are extensions provided by HLA.

6.6.6.5 The FSQRT Instruction

The fsqrt routine does not allow any operands. It computes the square root of the value on top of stack (TOS) and replaces ST0 with this result. The value on TOS must be zero or positive, otherwise fsqrt will generate an invalid operation exception.

This instruction can raise the stack, precision, denormalized, and invalid operation exceptions, as appropriate. If rounding occurs during the computation, fsqrt sets the C₁ condition code bit. If a stack fault exception occurs, C₁ denotes stack overflow or underflow.

Example:

 // Compute Z := sqrt(x**2 + y**2);           fld( x );            // Load X.           fld( st0 );          // Duplicate X on TOS.           fmul();              // Compute X**2.           fld( y );            // Load Y           fld( st0 );          // Duplicate Y.           fmul();              // Compute Y**2.           fadd();              // Compute X**2 + Y**2.           fsqrt();             // Compute sqrt( X**2 + Y**2 ).           fstp( z );           // Store result away into Z. 

6.6.6.6 The FPREM and FPREM1 Instructions

The fprem and fprem1 instructions compute a partial remainder. Intel designed the fprem instruction before the IEEE finalized its floating point standard. In the final draft of the IEEE floating point standard, the definition of fprem was a little different than Intel's original design. Unfortunately, Intel needed to maintain compatibility with the existing software that used the fprem instruction, so it designed a new version to handle the IEEE partial remainder operation, fprem1. You should always use fprem1 in new software you write; therefore we will only discuss fprem1 here, although you use fprem in an identical fashion.

fprem1 computes the partial remainder of ST0/ST1. If the difference between the exponents of ST0 and ST1 is less than 64, fprem1 can compute the exact remainder in one operation. Otherwise you will have to execute the fprem1 two or more times to get the correct remainder value. The C₂ condition code bit determines when the computation is complete. Note that fprem1 does not pop the two operands off the stack; it leaves the partial remainder in ST0 and the original divisor in ST1 in case you need to compute another partial product to complete the result.

The fprem1 instruction sets the stack exception flag if there aren't two values on the top of stack. It sets the underflow and denormal exception bits if the result is too small. It sets the invalid operation bit if the values on TOS are inappropriate for this operation. It sets the C₂ condition code bit if the partial remainder operation is not complete. Finally, it loads C₃, C₁, and C₀ with bits zero, one, and two of the quotient, respectively.

Example:

 // Compute Z := X mod Y           fld( y );           fld( x );           repeat                fprem1();                fstsw( ax );      // Get condition code bits into AX.                and( 1, ah );     // See if C2 is set.           until( @z );           // Repeat until C2 is clear.           fstp( z );             // Store away the remainder.           fstp( st0 );           // Pop old Y value. 

6.6.6.7 The FRNDINT Instruction

The frndint instruction rounds the value on the top of stack (TOS) to the nearest integer using the rounding algorithm specified in the control register.

This instruction sets the stack exception flag if there is no value on the TOS (it will also clear C₁ in this case). It sets the precision and denormal exception bits if there was a loss of precision. It sets the invalid operation flag if the value on the TOS is not a valid number. Note that the result on TOS is still a floating point value, it simply does not have a fractional component.

6.6.6.8 The FABS Instruction

fabs computes the absolute value of ST0 by clearing the mantissa sign bit of ST0. It sets the stack exception bit and invalid operation bits if the stack is empty.

Example:

 // Compute X := sqrt(abs(x));           fld( x );           fabs();           fsqrt();           fstp( x ); 

6.6.6.9 The FCHS Instruction

fchs changes the sign of ST0's value by inverting the mantissa sign bit (that is, this is the floating point negation instruction). It sets the stack exception bit and invalid operation bits if the stack is empty. Example:

 // Compute X := -X if X is positive, X := X if X is negative.           fld( x );           fabs();           fchs();           fstp( x ); 

6.6.7 Comparison Instructions

The FPU provides several instructions for comparing real values. The fcom, fcomp, and fcompp instructions compare the two values on the top of stack and set the condition codes appropriately. The ftst instruction compares the value on the top of stack with zero.

Generally, most programs test the condition code bits immediately after a comparison. Unfortunately, there are no FPU instructions that test the FPU condition codes. Instead, you use the fstsw instruction to copy the floating point status register into the AX register; then you can use the sahf instruction to copy the AH register into the 80x86's condition code bits. After doing this, you can test the standard 80x86 flags to check for some condition. This technique copies C₀ into the carry flag, C₂ into the parity flag, and C₃ into the zero flag. The sahf instruction does not copy C₁ into any of the 80x86's flag bits.

Because the sahf instruction does not copy any FPU status bits into the sign or overflow flags, you cannot use signed comparison instructions. Instead, use unsigned operations (e.g., seta, setb) when testing the results of a floating point comparison. Yes, these instructions normally test unsigned values, and floating point numbers are signed values. However, use the unsigned operations anyway; the fstsw and sahf instructions set the 80x86 flags register as though you had compared unsigned values with the cmp instruction.

The Pentium II and (upward) compatible processors provide an extra set of floating point comparison instructions that directly affect the 80x86 condition code flags. These instructions circumvent having to use fstsw and sahf to copy the FPU status into the 80x86 condition codes. These instructions include fcomi and fcomip. You use them just like the fcom and fcomp instructions except, of course, you do not have to manually copy the status bits to the flags register. Do be aware that these instructions are not available on all processors in common use today (as of 10/1/2002). However, as time passes it may be safe to begin assuming that everyone's CPU supports these instructions. Because this text assumes a minimum Pentium CPU, it will not discuss these two instructions any further.

6.6.7.1 The FCOM, FCOMP, and FCOMPP Instructions

The fcom, fcomp, and fcompp instructions compare ST0 to the specified operand and set the corresponding FPU condition code bits based on the result of the comparison. The legal forms for these instructions are

      fcom()      fcomp()      fcompp()      fcom( sti )      fcomp( sti )      fcom( mem_32_64 )      fcomp( mem_32_64 )      fcom( real_constant )      fcomp( real_constant ) 

With no operands, fcom, fcomp, and fcompp compare ST0 against ST1 and set the FPU flags accordingly. In addition, fcomp pops ST0 off the stack and fcompp pops both ST0 and ST1 off the stack.

With a single register operand, fcom and fcomp compare ST0 against the specified register. fcomp also pops ST0 after the comparison.

With a 32- or 64-bit memory operand, the fcom and fcomp instructions convert the memory variable to an 80-bit extended precision value and then compare ST0 against this value, setting the condition code bits accordingly. fcomp also pops ST0 after the comparison.

These instructions set C₂ (which winds up in the parity flag) if the two operands are not comparable (e.g., NaN). If it is possible for an illegal floating point value to wind up in a comparison, you should check the parity flag for an error before checking the desired condition (e.g., using HLA's @p and @np conditions, or by using the setp/setnp instructions).

These instructions set the stack fault bit if there aren't two items on the top of the register stack. They set the denormalized exception bit if either or both operands are denormalized. They set the invalid operation flag if either or both operands are quite NaNs. These instructions always clear the C1 condition code.

Note: The instructions that have real constants as operands aren't true FPU instructions. These are extensions provided by HLA. When HLA encounters such an instruction, it creates a real64 read-only variable in the constants segment and initializes this variable with the specified constant. Then HLA translates the instruction to one that specifies a real64 memory operand. Note that because of the precision differences (64 bits vs. 80 bits), if you use a constant operand in a floating point instruction you may not get results that are as precise as you would expect.

Example of a floating point comparison:

      fcompp();      fstsw( ax );      sahf();      setb( al ); // AL = true if ST1 < ST0.           .           .           . 

Note that you cannot compare floating point values in an HLA run-time boolean expression (e.g., within an if statement). You may, however, test the conditions in such statements after a floating point comparison like the sequence above, e.g.,

      fcompp();      fstsw( ax );      sahf();      if( @b ) then           << Code that executes if ST1 < ST0 >>      endif; 

6.6.7.2 The FTST Instruction

The ftst instruction compares the value in ST0 against 0.0. It behaves just like the fcom instruction would if ST1 contained 0.0. Note that this instruction does not differentiate -0.0 from +0.0. If the value in ST0 is either of these values, ftst will set C₃ to denote equality. Note that this instruction does not pop ST0 off the stack. Example:

      ftst();      fstsw( ax );      sahf();      sete( al );                     // Set AL to 1 if TOS = 0.0 

6.6.8 Constant Instructions

The FPU provides several instructions that let you load commonly used constants onto the FPU's register stack. These instructions set the stack fault, invalid operation, and C1 flags if a stack overflow occurs; they do not otherwise affect the FPU flags. The specific instructions in this category include:

      fldz()           ;Pushes +0.0.      fld1()           ;Pushes +1.0.      fldpi()          ;Pushes π.      fldl2t()         ;Pushes log2(10).      fldl2e()         ;Pushes log2(e).      fldlg2()         ;Pushes log10(2).      fldln2()         ;Pushes ln(2). 

6.6.9 Transcendental Instructions

The FPU provides eight transcendental (log and trigonometric) instructions to compute sin, cos, partial tangent, partial arctangent, 2x-1, y * log2(x), and y * log2(x+1). Using various algebraic identities, it is easy to compute most of the other common transcendental functions using these instructions.

6.6.9.1 The F2XM1 Instruction

f2xm1 computes 2^st0-1. The value in ST0 must be in the range −1.0<=ST0<=+1.0. If ST0 is out of range f2xm1 generates an undefined result but raises no exceptions. The computed value replaces the value in ST0. Example:

 ; Compute 10x using the identity: 10x = 2x*lg(10) (lg = log2).           fld( x );           fldl2t();           fmul();           f2xm1();           fld1();           fadd(); 

Note that f2xm1 computes 2^x−1, which is why the code above adds 1.0 to the result at the end of the computation.

6.6.9.2 The FSIN, FCOS, and FSINCOS Instructions

These instructions pop the value off the top of the register stack and compute the sine, cosine, or both, and push the result(s) back onto the stack. The fsincos pushes the sine followed by the cosine of the original operand; hence it leaves cos(ST0) in ST0 and sin(ST0) in ST1.

These instructions assume ST0 specifies an angle in radians, and this angle must be in the range −2⁶³< ST0 < +2⁶³. If the original operand is out of range, these instructions set the C₂ flag and leave ST0 unchanged. You can use the fprem1 instruction, with a divisor of 2π, to reduce the operand to a reasonable range.

These instructions set the stack fault/C₁, precision, underflow, denormalized, and invalid operation flags according to the result of the computation.

6.6.9.3 The FPTAN Instruction

fptan computers the tangent of ST0 and pushes this value and then it pushes 1.3 onto the stack. Like the fsin and fcos instructions, the value of ST0 must be in radians and in the range −2⁶³ <ST0<+2⁶³. If the value is outside this range, fptan sets C₂ to indicate that the conversion did not take place. As with the fsin, fcos, and fsincos instructions, you can use the fprem1 instruction to reduce this operand to a reasonable range using a divisor of 2π.

If the argument is invalid (i.e., zero or π radians, which causes a division by zero) the result is undefined and this instruction raises no exceptions. fptan will set the stack fault, precision, underflow, denormal, invalid operation, C₂, and C₁ bits as required by the operation.

6.6.9.4 The FPATAN Instruction

This instruction expects two values on the top of stack. It pops them and computes the following:

 ST0 = tan-1( ST1 / ST0 ) 

The resulting value is the arctangent of the ratio on the stack expressed in radians. If you have a value you wish to compute the arctangent of, use fld1 to create the appropriate ratio and then execute the fpatan instruction.

This instruction affects the stack fault/C₁, precision, underflow, denormal, and invalid operation bits if an problem occurs during the computation. It sets the C₁ condition code bit if it has to round the result.

6.6.9.5 The FYL2X Instruction

This instruction expects two operands on the FPU stack: y is found in ST1, and x is found in ST0. This function computes:

 ST0 = ST1 * log2( ST0 ) 

This instruction has no operands (to the instruction itself). The instruction uses the following syntax:

      fyl2x(); 

Note that this instruction computes the base two logarithm. Of course, it is a trivial matter to compute the log of any other base by multiplying by the appropriate constant.

6.6.9.6 The FYL2XP1 Instruction

This instruction expects two operands on the FPU stack: y is found in ST1, and x is found in ST0. This function computes:

 ST0 = ST1 * log2( ST0 + 1.0 ) 

The syntax for this instruction is

      fyl2xp1(); 

Otherwise, the instruction is identical to fyl2x.

6.6.10 Miscellaneous Instructions

The FPU includes several additional instructions which control the FPU, synchronize operations, and let you test or set various status bits. These instructions include finit/fninit, fldcw, fstcw, fclex/fnclex, and fstsw.

6.6.10.1 The FINIT and FNINIT Instructions

The finit instruction initializes the FPU for proper operation. Your applications should execute this instruction before executing any other FPU instructions. This instruction initializes the control register to $37F, the status register to zero, and the tag word to $FFFF. The other registers are unaffected. Examples:

      FINIT();      FNINIT(); 

The difference between finit and fninit is that finit first checks for any pending floating point exceptions before initializing the FPU; fninit does not.

6.6.10.2 The FLDCW and FSTCW Instructions

The fldcw and fstcw instructions require a single 16-bit memory operand:

      fldcw( mem_16 );      fstcw( mem_16 ); 

These two instructions load the control register from a memory location (fldcw) or store the control word to a 16-bit memory location (fstcw).

When using the fldcw instruction to turn on one of the exceptions, if the corresponding exception flag is set when you enable that exception, the FPU will generate an immediate interrupt before the CPU executes the next instruction. Therefore, you should use the fclex instruction to clear any pending interrupts before changing the FPU exception enable bits.

6.6.10.3 The FCLEX and FNCLEX Instructions

The fclex and fnclex instructions clear all exception bits the stack fault bit, and the busy flag in the FPU status register. Examples:

      fclex();      fnclex(); 

The difference between these instructions is the same as finit and fninit.

6.6.10.4 The FSTSW and FNSTSW Instructions

      fstsw( ax )      fnstsw( ax )      fstsw( mem_16 )      fnstsw( mem_16 ) 

These instructions store the FPU status register into a 16-bit memory location or the AX register. These instructions are unusual in the sense that they can copy an FPU value into one of the 80x86 general purpose registers (specifically, AX). Of course, the whole purpose behind allowing the transfer of the status register into AX is to allow the CPU to easily test the condition code register with the sahf instruction. The difference between fstsw and fnstsw is the same as for fclex and fnclex.

6.6.11 Integer Operations

The 80x87 FPUs provide special instructions that combine integer to extended precision conversion along with various arithmetic and comparison operations. These instructions are the following:

      fiadd( int_16_32 )      fisub( int_16_32 )      fisubr( int_16_32 )      fimul( int_16_32 )      fidiv( int_16_32 )      fidivr( int_16_32 )      ficom( int_16_32 )      ficomp( int_16_32 ) 

These instructions convert their 16- or 32-bit integer operands to an 80-bit extended precision floating point value and then use this value as the source operand for the specified operation. These instructions use ST0 as the destination operand.

^[2]Intel has also referred to this device as the Numeric Data Processor (NDP), Numeric Processor Extension (NPX), and math coprocessor.

^[3]Storing a denormalized value into a 32- or 64-bit memory variable will always set the underflow exception bit.