3.3. Logical Processors and Hyper-Threading Technology

Intel Xeon processors include two sets of registers, or architecture states, on a single core. This makes each physical processor act like two logical processors. The execution units and other resources within the core are shared by the two architecture states, enabling the processor to keep the execution units working more often. As a result, a processor with hyper-threading technology can increase performance 30% over the same processor without hyper-threading technology.

With hyper-threading technology, the two logical processors can execute different tasks, or threads, simultaneously using shared hardware resources. From a software or architecture perspective, this means operating systems and user programs can schedule threads to logical processors as they would on multiple physical processors. From a micro-architecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources. The result is that more transactions are processed, so many Internet and e-business applications see faster response times.

3.3.1 Thread Scheduling

Operating systems that recognize logical processors manage them as they do physical processors, scheduling tasks or threads to them. With more than one Xeon processor installed, operating systems can schedule threads to separate processors and separate logical processors on a single physical processor simultaneously, as shown in Figure 3-9.

Figure 3-9. Operating systems schedule threads to separate processors and to separate logical processors.

Because of the way the processors are counted and subsequently identified by the operating system, threads are always scheduled to logical processors on different physical processors before scheduling multiple threads to the same physical processor occurs. This optimization allows software threads to use different physical execution resources when possible.

The operating system disables a second logical processor when it is not needed by issuing a halt instruction. This prevents the second logical processor from repeatedly checking for work, which can consume significant execution resources.