Each trap type has a unique identifying number, which is used to modify the Trap Base Register and direct the CPU to the correct trap-handling routine. The types are assigned by the SPARC chip specification and correspond roughly to their priority. (Trap priorities only matter when simultaneous trap or interrupt requests are present). Some of these may become familiar to you after seeing some Bad Trap panics: a data fault , for instance, is trap type 9. The most common trap types and their meanings are listed below. Table 26-1. Common trap types
The first traps, up to the hardware interrupts, are synchronous: they are caused by or occur during an instruction. The various interrupt levels are asynchronous; level 15 is the highest priority. Software traps are those caused by the trap instruction, which has a type code from 0 to 127 embedded in the instruction as a constant or supplied in a register. Generally, only a few software trap codes are valid. One of them is used to issue system calls. (This code changed in Solaris 2, from a trap 0 to a trap 8 instruction. This enables the kernel to distinguish between system calls issued from statically linked SunOS 4.x binary executables and those issued from a Solaris 2 or Binary Compatibility library). Returning from trapsThe system must be able to return to the code that was interrupted or that caused the trap. There is one specific instruction, rett , which does a "return from trap" operation. This undoes the sequence of events that took place when the hardware recognized the trap. We've mentioned watchdog resets a few times now. Let's move on to the next chapter where we discuss them in greater detail. |