20.

Finite State Machine Implementation



Genius is 1% inspiration and 99% perspiration.
-T. Edison

Faultily faultless, icily regular, splendidly null,
Dead perfection, no more.
-Alfred, Lord Tennyson



Introduction

Once we have the logic equations for the next-state and output functions, the final step is to choose a method for their implementation. In the previous chapter, we assumed that the implementation method was based on discrete logic, such as TTL SSI gates. However, there are many alternative approaches based on higher levels of integration. These ex-ploit MSI parts, such as counters/multiplexers/decoders, or programmable logic components like PALs/PLAs and ROMs. Programmable logic allows us to implement more complex finite state machines with dramatically fewer components.

Especially important is a new class of digital components, called field-programmable gate arrays (FPGAs). A gate array is a com-po-nent that contains a large number of gates whose function and interconnect are initially uncommitted. Field programmable means that you can determine the function and interconnect "in the field" rather than when the parts are manufactured. You can even reprogram these components to revise their function or specify a new function altogether.

Many FPGAs combine flip-flops with discrete gates, making it possible to construct a complete finite state machine on a chip. They combine the economy of discrete gate designs with the dense integration and low parts count of programmable logic. Furthermore, they provide the key hardware technology for rapid prototyping: Given a logic description and the appropriate CAD tools, you can personalize or program an FPGA in fractions of a second.

In this chapter, we will examine the techniques for implementing finite state machines using MSI components and programmable logic. In particular, you will learn how to:
  • Implement state machines with ROMs or PALs/PLAs. The next-state and output functions are implemented with programmable logic connected to state flip-flops.

  • Use MSI components to reduce component counts. The next-state and output functions can be implemented with multiplexers and decoders, and counters can be used as the state register.

  • Use field-programmable gate arrays. You will see how to use devices like the Altera electronically programmed logic devices (EPLDs), Actel field-programmable gate arrays (FPGAs), and Xilinx logic cell arrays (LCAs) to implement finite state machines in a minimum number of components.

Table of Contents

1. Finite State Machine Design with Programmable Logic
2. FSM Design with Counters
3. FSM Design with More Sophisticated Programmable Logic Devices
Chapter Review
Exercises

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This file last updated on 07/15/96 at 21:30:30.
randy@cs.Berkeley.edu;


What is Sarbanes-Oxley[q]
What is Sarbanes-Oxley[q]
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