List of Figures

Chapter 1: Hello, World of Assembly Language

Figure 1-1: Basic HLA Program.

Figure 1-2: Static Variable Declarations.

Figure 1-3: Static Variable Initialization.

Figure 1-4: Von Neumann Computer System Block Diagram.

Figure 1-5: 80x86 (Intel CPU) General Purpose Registers.

Figure 1-6: Layout of the Flags Register (Lower 16 Bits of EFLAGS).

Figure 1-7: Memory Write Operation.

Figure 1-8: Memory Read Operation.

Figure 1-9: Byte, Word, and Double Word Storage in Memory.

Figure 1-10: HLA IF Statement Syntax.

Figure 1-11: HLA WHILE Statement Syntax.

Figure 1-12: HLA REPEAT..UNTIL Statement Syntax.

Figure 1-13: HLA BREAK and BREAKIF Syntax.

Figure 1-14: HLA FOREVER Loop Syntax.

Figure 1-15: HLA TRY..EXCEPTION..ENDTRY Statement Syntax.

Chapter 2: Data Representation

Figure 2-1: Bit Numbering.

Figure 2-2: The Two Nibbles in a Byte.

Figure 2-3: Bit Numbers in a Word.

Figure 2-4: The Two Bytes in a Word.

Figure 2-5: Nibbles in a Word.

Figure 2-6: Bit Numbers in a Double Word.

Figure 2-7: Nibbles, Bytes, and Words in a Double Word.

Figure 2-8: Shift Left Operation.

Figure 2-9: Shift Left Operation.

Figure 2-10: Shift Right Operation.

Figure 2-11: Shift Right Operation.

Figure 2-12: Arithmetic Shift Right Operation.

Figure 2-13: SAR( 1, dest ) Operation.

Figure 2-14: Rotate Left Operation.

Figure 2-15: Rotate Right Operation.

Figure 2-16: ROL( 1, Dest ) Operation.

Figure 2-17: ROR( 1, Dest ) Operation.

Figure 2-18: RCL( 1, Dest ) Operation.

Figure 2-19: RCR( 1, Dest ) Operation.

Figure 2-20: Short Packed Date Format (Two Bytes).

Figure 2-21: Long Packed Date Format (Four Bytes).

Figure 2-22: Layout of the flags register.

Figure 2-23: Long Packed Date Format (Four Bytes).

Figure 2-24: Single Precision (32-bit) Floating Point Format

Figure 2-25: 64-Bit Double Precision Floating Point Format.

Figure 2-26: 80-Bit Extended Precision Floating Point Format.

Figure 2-27: BCD Data Representation in Memory.

Figure 2-28: ASCII Codes for "E" and "e."

Chapter 3: Memory Access and Organization

Figure 3-1: Displacement-Only (Direct) Addressing Mode.

Figure 3-2: Accessing a Word or DWord Using the Displacement Only Addressing Mode.

Figure 3-3: Indexed Addressing Mode.

Figure 3-4: Indexed Addressing Mode Using a Register Plus a Constant.

Figure 3-5: Indexed Addressing Mode Using a Register Minus a Constant.

Figure 3-6: The Scaled Indexed Addressing Mode.

Figure 3-7: HLA Typical Run-Time Memory Organization.

Figure 3-8: Using an Address Expression to Access Data Beyond a Variable.

Figure 3-9: Before "PUSH( EAX );" Operation.

Figure 3-10: Stack Segment After "PUSH( EAX );" Operation.

Figure 3-11: Memory Before a "POP( EAX );" Operation.

Figure 3-12: Memory After the "POP( EAX );" Instruction.

Figure 3-13: Stack After Pushing EAX.

Figure 3-14: Stack After Pushing EBX.

Figure 3-15: Stack After Popping EAX.

Figure 3-16: Stack After Popping EBX.

Figure 3-17: Removing Data from the Stack, Before ADD( 8, ESP ).

Figure 3-18: Removing Data from the Stack, After ADD( 8, ESP ).

Figure 3-19: Stack After Pushing EAX and EBX.

Figure 3-20: Call to malloc Returns a Pointer in the EAX Register.

Figure 3-21: Allocating a Sequence of Eight-Character Objects Using Malloc.

Chapter 4: Constants, Variables, and Data Types

Figure 4-1: Incorrectly Indexing off a String Variable.

Figure 4-2: Correctly Indexing off the Value of a String Variable.

Figure 4-3: Bit Layout of a Character Set Object.

Figure 4-4: Array Layout in Memory.

Figure 4-5: Mapping a 4x4 Array to Sequential Memory Locations.

Figure 4-6: Row Major Array Element Ordering.

Figure 4-7: Another View of Row Major Ordering for a 4x4 Array.

Figure 4-8: Viewing a 4x4 Array as an Array of Arrays.

Figure 4-9: Column Major Array Element Ordering.

Figure 4-10: Student Data Structure Storage in Memory.

Figure 4-11: Layout of a UNION vs. a RECORD Variable.

Chapter 5: Procedures and Units

Figure 5-1: Stack Contents Before RET in "MessedUp" Procedure.

Figure 5-2: Stack Contents Before RET in MessedUpToo.

Figure 5-3: Stack Organization Immediately Upon Entry into ARDemo.

Figure 5-4: Activation Record for ARDemo.

Figure 5-5: Offsets of Objects in the ARDemo Activation Record.

Figure 5-6: Activation Record for LocalVars Procedure.

Figure 5-7: Stack Layout upon Entry into CallProc.

Figure 5-8: Activation Record for CallProc After Standard Entry Sequence Execution.

Figure 5-9: OneByteParm Activation Record.

Figure 5-10: Using Header Files in HLA Programs.

Chapter 6: Arithmetic

Figure 6-1: FPU Floating Point Register Stack.

Figure 6-2: FPU Control Register.

Figure 6-3: The FPU Status Register.

Figure 6-4: FPU Floating Point Formats.

Figure 6-5: FPU Integer Formats.

Figure 6-6: FPU Packed Decimal Format.

Chapter 7: Low Level Control Structures

Figure 7-1: IF..THEN..ELSE..ENDIF and IF..ENDIF Statement Flow.

Figure 7-2: CONTINUE Destination for the FOREVER Loop.

Figure 7-3: CONTINUE Destination and the WHILE Loop.

Figure 7-4: CONTINUE Destination and the FOR Loop.

Figure 7-5: CONTINUE Destination and the REPEAT..UNTIL Loop.

Chapter 8: Files

Figure 8-1: Fixed Length Format for Person Record.

Figure 8-2: Variable Length Format for Person Record.

Chapter 9: Advanced Arithmetic

Figure 9-1: Adding Two 96-Bit Objects Together.

Figure 9-2: Extended Precision Multiplication.

Figure 9-3: Manual Digit-by-digit Division Operation.

Figure 9-4: Longhand Division in Binary.

Figure 9-5: 64-Bit Shift Left Operation.

Figure 9-6: SHLD Operation.

Figure 9-7: SHRD Operation.

Chapter 10: Macros and the HLA Compile Time Language

Figure 10-1: Compile Time Versus Run-Time Execution.

Figure 10-2: Operation of HLA Compile Time #IF Statement.

Figure 10-3: HLA Compile Time #WHILE Statement Operation.

Chapter 11: BIT Manipulation

Figure 11-1: Isolating a Bit String Using the AND Instruction.

Figure 11-2: Inserting Bits 0..12 of EAX into Bits 12..24 of EBX.

Figure 11-3: Inserting a Bit String into a Destination Operand.

Chapter 12: The String Instructions

Figure 12-1: Copying Data Between Two Overlapping Arrays (Forward Direction).

Figure 12-2: Using a Backward Copy to Copy Data in Overlapping Arrays.

Chapter 13: The MMX Instruction Set

Figure 13-1: MMX and FPU Register Aliasing.

Figure 13-2: The MMX Data Types.

Figure 13-3: PACKSSDW Instruction.

Figure 13-4: PACKSSWB Instruction.

Figure 13-5: PUNPCKLBW Instruction.

Figure 13-6: PUNPCKLWD Instruction.

Figure 13-7: PUNPCKLDQ Instruction.

Figure 13-8: PUNPCKHBW Instruction.

Figure 13-9: PUNPCKHWD Instruction.

Figure 13-10: PUNPCKDQ Instruction.

Figure 13-11: PCMPEQB and PCMPGTB Instructions.

Figure 13-12: PCMPEQW and PCMPGTW Instructions.

Figure 13-13: PCMPEQD and PCMPGTD Instructions.

Chapter 14: Classes and Objects

Figure 14-1: Student RECORD Implementation in Memory.

Figure 14-2: Student CLASS Implementation in Memory.

Figure 14-3: Object Allocation with Static Data Fields.

Figure 14-4: Virtual Method Table Organization.

Figure 14-5: All Objects That Are the Same Class Type Share the Same VMT.

Figure 14-6: Layout of Base and Child Class Objects in Memory.

Figure 14-7: Virtual Method Table References from Objects.

Figure 14-8: Virtual Method Tables for Inherited Classes.