Chapter 3. Signal Groups

The Previous Chapter

The previous chapter provided an overview of the HT architecture that defines the primary elements of HT technology and the relationship between these elements. The chapter summarized the features, capabilities, and limitation of HT and provided the background information necessary for in-depth discussions of the various HT topics in later chapters.

This Chapter

This chapter describes the function of each signal in the high and low speed HyperTransport signal groups. The CAD, CTL, and CLK high speed signals are routed point-to-point as low-voltage differential pairs between two devices (or between a device and a connector in some cases). The RESET#, PWROK, LDTREQ#, and LDTSTOP# low speed signals are single-ended low voltage CMOS and may be bused to multiple devices. In addition, each device requires power supply and ground pins. Because the CAD bus width is scalable, the actual number of CAD and CLK signal pairs varies, as does the number of power and ground pins to the device.

The Next Chapter

The next chapter describes the use of HyperTransport control and data packets to construct HyperTransport link transactions. Control packet types include Information, Request, and Response variants; data packets contain a payload of 0-64 valid bytes. The transmission, structure, and use of each packet type is presented.