SCSI Parallel Interface
| This section explores the details of SPI operation. Though the SPI is waning in popularity, there is still a significant amount of SPI-connected storage in production environments today. SPI Media, Connectors, Transceivers, and Operating RangesThe SPI supports only copper media, but various copper media and connectors can be used depending on the SPI version. Media and connectors are specified as shielded or unshielded. Shielded components are used for external connections between enclosures, and unshielded components are used for connections inside an enclosure. Table 5-1 summarizes the supported configurations for each SPI version.
As discussed in chapter 3, "Overview of Network Operating Principles," the SPI uses four transceiver types known as single-ended (SE), multimode single-ended (MSE), low voltage differential (LVD), and high voltage differential (HVD). The SPI operating range is determined by the transceiver type, the medium, the number of attached devices, and the data rate. Table 5-2 summarizes the operating range (expressed in meters) supported by each SPI version.
SPI Encoding and SignalingAs explained in chapter 3, "Overview of Network Operating Principles," many networking technologies encode data bits received from OSI Layer 2 into a different bit set before transmission at OSI Layer 1. However, the SPI does not. Instead, the SPI implements a complex system of electrical signaling at OSI Layer 1 to provide similar functionality. The SPI implements multiple electrical signaling schemes depending on the transceiver type, data transfer mode, and data rate. Additionally, the SPI electrical signaling schemes provide much of the OSI Layer 2 functionality that is normally provided via control frames and header fields. Several different electrical signals are raised and lowered in concert to maintain clock synchronization, negotiate bus phases, establish peer sessions, control the flow of data, recover from bus errors, and so on. This approach reflects the parallel nature of the SPI. Because this approach is quite different from the methods employed by serial networking technologies, in-depth discussion of the SPI signaling rules is not germane to the understanding of modern storage networks. Readers who are interested in these details are encouraged to consult the latest version of the ANSI T10 SPI specification. SPI Addressing SchemeThe SPI does not implement any equivalent to SAM device or port names. However, the SPI does implement an equivalent to SAM port identifiers. These are known simply as SCSI Identifiers (SCSI IDs). SPI devices use SCSI IDs when transmitting frames to indicate the intended destination device. On an 8-bit wide data bus, up to eight SCSI IDs are supported ranging from 0 to 7. On a 16-bit wide data bus, up to 16 SCSI IDs are supported ranging from 0 to 15. SPI Name Assignment and ResolutionThe SPI does not implement SAM names, so name assignment and resolution mechanisms are not required. SPI Address Assignment and ResolutionThe SCSI ID of each device must be manually configured. An SPI device typically has a jumper block, toggle-switch block, or other physical selector that is used to configure the SCSI ID. Some storage controllers support software-based SCSI ID configuration via a setup program embedded in the controller's BIOS. A protocol called SCSI configured automatically (SCAM) was defined in SPI-2 for automatic SCSI ID assignment on SPI buses. SCAM promised to bring plug-and-play functionality to the SPI. However, SPI-3 made SCAM obsolete, thus preserving the static nature of SCSI IDs. The SPI implements only OSI Layer 2 addresses, so address resolution is not required. SPI Media AccessBecause all SPI attached devices use a common set of pins for transmission and reception, only one device can transmit at any point in time. Media access is facilitated through an arbitration process. Each device is assigned an arbitration priority based on its SCSI ID. The highest priority is 1, which is always assigned to SCSI ID 7. Typically, only one initiator is attached to an SPI bus, and it is assigned SCSI ID 7 by convention. This convention ensures the initiator is able to take control of the bus at any time. For historical reasons, the remaining priority assignments are not as straightforward as one might expect. Table 5-3 lists the SPI priorities and associated SCSI IDs.
Note It is possible for multiple initiators to be connected to a single SPI bus. Such a configuration is used for clustering solutions, in which multiple hosts need simultaneous access to a common set of LUNs. However, most SPI bus deployments are single initiator configurations. There are two methods of arbitration; normal arbitration, and quick arbitration and selection (QAS). Normal arbitration must be supported by every device, but QAS support is optional. QAS can be negotiated between pairs of devices, thus allowing each device to use normal arbitration to communicate with some devices and QAS arbitration to communicate with other devices. This enables simultaneous support of QAS-enabled devices and non-QAS devices on a single SPI bus. Using normal arbitration, priority determines which device gains access to the bus if more than one device simultaneously requests access. Each device that loses an arbitration attempt simply retries at the next arbitration interval. Each device continues retrying until no higher priority devices simultaneously arbitrate, at which point the lower priority device can transmit. This can result in starvation of low-priority devices. So, an optional fairness algorithm is supported to prevent starvation. When fairness is used, each device maintains a record of arbitration attempts. Higher priority devices are allowed to access the bus first, but are restrained from arbitrating again until lower priority devices that lost previous arbitration attempts are allowed to access the bus. The intricacies of this arbitration model can be illustrated with an analogy. Suppose that a director of a corporation goes to the company's cafeteria for lunch and arrives at the cashier line at precisely the same time as a vice president. The director must allow the vice president to go ahead based on rank. Now suppose that the corporation's president arrives. The president must get in line behind the director despite the president's superior rank. Also, the director may not turn around to schmooze with the president (despite the director's innate desire to schmooze upwardly). Thus, the director cannot offer to let the president go ahead. However, the director can step out of line (for example, to swap a chocolate whole milk for a plain low-fat milk). If the director is out of line long enough for the cashier to service one or more patrons, the director must re-enter the line behind all other employees. QAS is essentially normal arbitration with a streamlined method for detecting when the bus is available for a new arbitration attempt. Normal arbitration requires the SPI bus to transition into the BUS FREE phase before a new arbitration attempt can occur. QAS allows a QAS-enabled device to take control of the bus from another QAS-enabled device without changing to BUS FREE. To prevent starvation of non-QAS-enabled devices, the initiator can arbitrate via QAS and, upon winning, force a BUS FREE transition to occur. Normal arbitration must then be used by all devices for the ensuing arbitration cycle. In this respect, the convention of assigning the highest priority to the initiator allows the initiator to police the bus. The fairness algorithm is mandatory for all QAS-enabled devices when using QAS, but it is optional for QAS-enabled devices during normal arbitration. SPI Network BoundariesAll SPI bus implementations are physically bounded. It is not possible to create an internetwork of SPI buses because no OSI Layer 2 bridging capability is defined. Therefore, the SPI does not support logical boundaries. Likewise, the concept of a virtual SPI bus is not defined in any specification. Note that it is possible to expand a single SPI bus via SCSI expanders that provide OSI Layer 1 repeater functionality. In fact, some SCSI enclosures employ an expander between each pair of drives to facilitate hot-pluggable operation. However, SPI expanders do not affect the operation of an SPI bus at OSI Layer 2. Therefore, an SPI bus is always a single physical segment bounded by its terminators. SPI Frame FormatsThe SPI implements various frame formats, each of which is used during a specific bus phase. Three frame formats are defined for the DATA phase: data, data group, and information unit. The frame format used depends on the data transfer mode. During asynchronous transfer, only the data format may be used. During synchronous transfers, the data, data group, and information unit formats may be used. During paced transfer, only the information unit format may be used. During asynchronous transfer, only data is transmitted. There is no header or trailer. There is no formal frame format aside from stipulated bit and byte positions for data. A separate electrical signal is used to indicate odd parity for the data bits. By contrast, a data group frame has a data field, an optional pad field and a parallel CRC (pCRC) trailer field. Likewise, an information unit frame has a data field, an optional pad field, and an information unit CRC (iuCRC) trailer field. The difference between a data group and an information unit has less to do with frame format than with protocol behavior during data transfer. SPI Delivery MechanismsThe SPI represents a very simple network. So, delivery mechanisms are inherently simplified. The SPI implements the following delivery mechanisms:
SPI Link AggregationThe SPI-2 specification supported link aggregation as a means of doubling the data bus width from 16 bits to 32 bits. Link aggregation can be tricky even with serial links, so it is impressive that the ANSI T10 subcommittee defined a means to aggregate parallel links. The limited distance and single-segment nature of the SPI simplified some aspects of the SPI link aggregation scheme, which made ANSI's job a bit easier. The SPI 32-bit data bus signals were spread across two parallel links to load-balance at the byte level. The parallel nature of the SPI made byte-level load balancing possible. The SPI 32-bit data bus was made obsolete by SPI-3. No subsequent SPI specification defines a new link-aggregation technique. SPI Link InitializationThe SPI bus is itself a cable. Therefore, initialization of an SPI bus is actually initialization of the devices attached to the bus. Therefore, SPI bus initialization cannot begin until one or more devices power on. The bus phase is BUS FREE after devices power on until an initiator begins target discovery. As described in chapter 3, "Overview of Network Operating Principles," target discovery is accomplished via the TEST UNIT READY and INQUIRY commands. Upon completing its internal power-on self test (POST), a target device is capable of responding to the TEST UNIT READY and INQUIRY commands. Upon completing its internal POST, a initiator device is capable of issuing the TEST UNIT READY and INQUIRY commands. To initiate these commands, the initiator must arbitrate for access to the bus. During initial arbitration, only the initiator attempts bus access. Upon winning arbitration, target discovery ensues as described in chapter 3, "Overview of Network Operating Principles." After target discovery completes, normal bus communication ensues. |
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