4.3 Some Tips and Guidelines for Physical Design

   

The following are some guidelines for hierarchical design structures. For designs larger than two million gates, some hierarchical plus partitioned design methodology should be used. The fact that parallel processing is performed makes hierarchical methodology an attractive implementation for physical designs.

Use Placement-Based Synthesis

As we discussed in Chapter 2 for designs larger than two million gates, a placement-based synthesis approach must be taken. Figure 4.4 shows the design flow for a placement-based synthesis.

Figure 4.4. Design Flow with Placement-Based Synthesis

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Logical versus Physical Hierarchy

In a hierarchical design, initially you can have an unlimited number of hierarchies in your logic design. However, after generating a floor-plan with a chip-level timing budget, logical hierarchy should match the physical hierarchy. Setting the timing budgets for each block in your design and making sure that you haven't overconstrained certain blocks while underconstraining others are important points to consider.

Figure 4.5 shows that the logical hierarchy matches the physical hierarchy. Here hierarchical layout block (HLB) is a block that can be laid out independently as a hard macro.

Figure 4.5. Logical versus Physical Hierarchy (Printed with permission of Fujitsu Microelectronics America, Inc.)

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Clock Design

Figure 4.6 shows a two-level clock-tree design where you have chip-level and block-level clocks. Apply the following for your clock implementation:

  1. Chip-level clock tree

    Designers should prepare only one clock-tree block at the Level_0. This level of hierarchy consists of HLB, clock block, and repeater cell .

  2. Block-level clock tree

    Designers should prepare only one clock-tree block at the Level_1 (block level). Do not distribute the block-level clock to other blocks.

  3. Clock balancing with upper and lower blocks

    Designers should take care of clock balancing between Level_0 and Level_1.

Figure 4.6. Two-Level Clock-Tree Design (Printed with permission of Fujitsu Microelectronics America, Inc.)

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Global Bus Design

Figure 4.7 shows an example of a global bus design.

  1. Logic designers must control the bus-switch logic based on the floorplan.

  2. Do not use tri-state buffers for chip-level bus, for the following reasons:

    Cannot insert a repeater cell

    Cannot drive a high capacitance bus load

  3. Allowing for bus switch logic placement, you should resynthesis or redesign the bus switch logic as well as the bus-arbitration logic.

Figure 4.7. Global Bus Design (Printed with permission of Fujitsu Microelectronics America, Inc.)

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Multiple Placements and Routing

When using hierarchical methodology, it is best to use multiple placements and routing, as shown in Figure 4.8. The first place and route will require an estimate for the location of your blocks. All subsequent placement and routing stages are based on fixed-block assignments and adjusting I/O positions .

Figure 4.8. Multiple Placements and Routing in a Hierarchical Methodology

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Nonroutable Congested Areas

Apply the following when you experience a nonroutable congestion in your design:

  1. Change the aspect ratio.

  2. Change the distance between the blocks/macros.

  3. Allow the routing over the block.

  4. Change the location of the block/macro.

  5. Go back to the initial placement again.


   
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From ASICs to SOCs. A Practical Approach
From ASICs to SOCs: A Practical Approach
ISBN: 0130338575
EAN: 2147483647
Year: 2003
Pages: 61

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