Background

Several x86 processor-specific features require support for both hardware and software compatibility, including:

• A method for supporting x86 CPU legacy signals

• A method for supporting x86 Special Cycles

• x86 legacy interrupt support ” PCI (8259) and APIC

• Power Management

Other legacy issues related to Industry Standard Architecture (ISA) platforms deal with I/O bus compatibility, rather than processor- related issues. These topics are discussed in the chapter entitled, "I/O Compatibility."

Legacy Signals

Support for the features mentioned above involves a number of X86 signals. These signals include those preserved throughout the x86 processor evolution to maintain compatibility:

• INTR (Interrupt Request from the 8259 Interrupt Controllers)

• APIC bus (Advanced Programmable Interrupt Controller bus)

• A20M (Processor Address Line A20 Mask)

• SMI (System Management Interrupt)

• SMIACT (System Management Interrupt Active)

• STPCLK (Stop Clock)

• FERR (Floating-Point Error)

• IGNNE (Ignore Numeric Error)

Figure 22-1 on page 492 illustrates the typical implementation of these signals in a non-HT system. Note that these signals are typically routed directly between the CPU and South bridge in a legacy platform with PCI.

Figure 22-1. CPU Signals Routed Between South Bridge and CPU

Legacy Special Cycles

Some x86 CPU events are signaled via special cycles. The CPU uses its system interface (e.g. front-side bus) to signal special cycles to the Host Bridge. The events signaled by an x86 CPU include:

• SHUTDOWN

• HALT

• INTA (Interrupt Acknowledge)

• STOP_GRANT

• Voltage ID/Frequency ID Change (Athlon processor)

• WBINVD (write-back and invalidate)

• INVD (invalidate)

Special cycles have various jobs related to x86 functions such as Interrupts, System Management Mode (SMM), power management, and cache coherency.

Note that each of the x86 signals and special cycles are discussed within the section that describes the x86 function to which the signal or special cycle relates .

System Management Messages

HyperTransport eliminates the direct signal routing between the x86 CPU and the compatibility bridge (South Bridge, ICH, etc.) used in legacy platforms. Instead, HT defines System Management (SM) requests that serve to convey information that otherwise would be conveyed via signals. These messages act as virtual wires that signal INTR, FERR#, IGNNE#, A20M#, STPCLK#, SMI# and SMIACT#. Note that the default state of virtual wires is deasserted. Figure 22-2 on page 494 illustrates that messages may move in either direction.

Figure 22-2. SM Request Sources

Delivery of special cycle messages is also done via SM messages. When the Host Bridge receives a special cycle from the CPU, it sends an SM message that delivers the special cycle message to interested parties residing on the HT bus. Refer to Chapter 22, entitled "X86 CPU Compatibility," on page 491 for a detailed explanation of the SM messages.