DMA Mapping

Expansion bus master accesses to memory may need to target HT and main memory locations that are beyond the range of the expansion bus. Five registers within the address remapping block combine to define one or more DMA mappings within HT address space. Each DMA mapping is intended to provide a separate range of memory space for each bus master on the expansion bus. Note also that the corresponding DMA Control field enables or disables each DMA mapping range. The definition and use of each DMA register is defined below.

Number of DMA Mappings

This read-only register defines the number of DMA mappings implemented by the bridge. The specification recommends that one set of DMA fields be allocated for each device (bus master) on the expansion bus that can access system memory. The HT specification suggests that HyperTransport-to-PCI bridges, support at least one mapping per REQ/GNT pair.

DMA Secondary Base N and DMA Secondary Limit N

These fields, when enabled, define a range of expansion bus memory space used by a bus master when accessing memory locations upstream. These registers specify a range of addresses in 16MB blocks. Each DMA secondary base and DMA secondary limit field defines address bit 39:24. The lower 24 address bits of the secondary base are specified to be all zeros and the lower address bits of the limit register are specified to be all ones, thereby creating a minimum address range of 16MB when the base and limit values are the same. Note, also, that the upper bits these fields will not be used if the expansion bus address is smaller than HT address space.

DMA Primary Base N

The DMA primary base field defines the base HT address where the address within the expansion bus DMA address range is to be mapped. The format of this field is the same as the DMA base field. The HT address is formed by adding the difference between the primary base and secondary base values to the actual address.

DMA Control Field

In addition to the DMA enable/disable function, the DMA Control field also establishes HT attributes associated with DMA accesses. Expansion bus masters may not define attributes that are supported by HT. The DMA control register permits software to define characteristics and attributes associated with each DMA address range. Figure 21-8 on page 490 illustrates the format and defines each bit of the DMA Control field.

• Enable ” permits software to enable or disable a range of DMA address space

• Isochronous ” specifies that this DMA range is associated with Isochronous transfers

• NonCoherent ” indicates that this range of address space is not cacheable

Figure 21-8. DMA Control Field