2.10 The Beowulf Challenge

		not mean that you have to assemble the system yourself. Many system integrators, both large and small, will assemble custom systems for little or no price premium. In fact, every system they assemble is from component parts, so a custom system is no more difficult for them than a standard one.

		There is an enormous diversity of choice both in type and quantity of components. There is more than one microprocessor family to consider and within each family multiple versions. There is flexibility in both the amount and type of main memory. Disk drives, too, offer a range of interface, speed, capacity, and number. Choices concerning ancillary elements such as floppy disk drives and CD-ROM drives have to be considered. Moreover, the choice of the motherboard and its chip set provide yet another dimension to PC node implementation. This chapter examines each of these issues individually and considers their interrelationships. A step-by-step procedure for the assembly of a processor node is provided to guide the initiate and protect the overconfident.

		Finally, we reiterate that we make no attempt to offer a complete or exhaustive survey. There are far more products available than can be explicitly presented in any single book, and new products are being offered all the time. However, in spite of the impossibility of exhaustive coverage, the information provided here should contain most of what is required to implement a Beowulf node. Final details can be acquired from documentation provided by the parts vendors.

		3.1 Overview of a Beowulf Node

		The Beowulf node is responsible for all activities and capabilities associated with executing an application program and supporting a sophisticated software environment. These fall into four general categories:

		1. Instruction Execution,

		2. High speed temporary information storage,

		3. High capacity persistent information storage,

		4. Communication with the external environment, including other nodes.

		The node is responsible for performing a set of designated instructions specified by the application program code or system software. The lowest level binary encoding of the instructions and the actions they perform are dictated by the microprocessor Instruction Set Architecture (ISA). Both the instructions and the data upon which they act are stored in and loaded from the node's random access memory (RAM). The speed of a processor is often measured in MHz, indicating that its clock ticks so