D.7 State Management Registers

Some combination of hardware and software must manage all sorts of state transitions in a system, including those related to function calling at the level of application programming and those related to the management of threads, processes, and interrupts.

In general, memory stacks are usually chosen as the means of preserving information about a prior state for restoration later. The Itanium architecture can preserve one level of prior state information in hardware in the application register called ar.pfs (previous function state register), whose general structure is as follows:

graphics/dfig07.gif

where ppl is the previous value of the privilege level copied from the processor status register (Section D.9), pec is the previous value of the epilog counter copied from ar.ec, and pfm is the previous frame marker copied from cfm, the current frame marker (discussed next).

This register preserves and restores those three elements of current state information automatically during call and return instructions. Leaf functions can thus be simple; more generally, nonleaf functions must preserve and restore pfs. Note that even leaf functions may need to preserve ar.lc, the loop counter.

The cfm (current frame marker) describes how the stacked general registers are partitioned for the current program, procedure, or function. It also provides the place where the hardware manages the rotating subset of the general, predicate, and floating-point registers.

graphics/dfig08.gif

The so- (size of) fields of cfm are modified indirectly through the alloc instruction, and the rrb (rotating register base) fields of cfm are modified indirectly through the branch instructions for loop control and for calling and returning from procedures or functions.

The um (user mask) contains the lowest six bits out of the processor status register (psr, Section D.9). These bits are control and status flags that are described in Table D-6.

Table D-6. Definitions of Processor Status Bits

Bit

Name

Type

Description

0

  

Reserved

1

psr.be

Control

0: little-endian byte order for memory access

1: big-endian byte order for memory access

2

psr.up

Control

0: user performance monitors are off

1: user performance monitors are enabled

3

psr.ac

Control

0: unaligned memory access may generate a fault

1: unaligned memory access must generate a fault

4

psr.mfl

Status

Set if any lower (Fr0 Fr31) floating-point registers have been written. The bit must be explicitly cleared.

5

psr.mfh

Status

Set if any higher (Fr32 Fr127) floating-point registers have been written. The bit must be explicitly cleared.

Special instructions are provided to reset (rum) and set (sum) groups of bits in the user mask, and to read or write the entire user mask (mov um).



ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ISBN: N/A
EAN: N/A
Year: 2003
Pages: 223

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