D.6 Application Registers

The Itanium architecture provides for defining up to 128 application registers (Ar₀ Ar₁₂₇), which are 64 bits in width and can thus accommodate address pointers and either signed or unsigned integers of that size:

These registers perform specific tasks in association with various instructions and operations in application-level software running on an Itanium system.

Table D-4. Itanium Floating-Point Registers

Register	Assembler Name	Other Name	Class	Usage Notes
Fr0	f0		Constant	Always +0.0; writes illegal
Fr1	f1		Constant	Always +1.0; writes illegal
Fr2 Fr5	f2 f5		Preserved
Fr6 Fr7	f6 f7		Scratch
Fr8 Fr15	f8 f15		Scratch	Floating-point arguments to a function and values returned by a function
Fr16 Fr31	f16 f31		Preserved
Fr32 Fr127	f32 f127		Scratch	Rotating registers

Table D-5 gives the nomenclature and standardized uses of currently defined Itanium application registers. Undefined registers are denoted as either reserved or ignored. Attempted access to a reserved register causes an illegal operation fault. A read operation on an ignored register will return zero; a write operation on an ignored register will have no effect.

The column headed Unit indicates with I or M whether the instruction to access a particular register must be mov.i or mov.m or either.

A register is read-only if its value is dynamically maintained at the hardware level or by the operating system, but cannot be modified by an application program. A register is special if it has some purpose assigned to it, either at the hardware level or by software convention. A register is scratch if it may be freely used by a routine at any calling level (caller must save anything important). A register is preserved if a calling routine depends on its contents (any called procedure must save and restore its contents for its caller). A register is automatic if its name (number) only has a dynamic correspondence to a physical register; such registers are automatically spilled to and filled from memory at allocation times by the hardware, as necessary.

Table D-5. Itanium Application Registers

Register	Assembler Name	Other Name	Unit	Class	Usage Notes
Ar0 Ar7	ar.k0 ar.k7	Kr0 Kr7	M	Read-only	Kernel registers
Ar8 Ar15			M		Reserved
Ar16	ar.rsc		M	Special	Register stack configuration
Ar17	ar.bsp		M	Read-only	Backing store pointer
Ar18	ar.bspstore		M	Special	Backing store "store" pointer
Ar19	ar.rnat		M	Automatic	RSE NaT collection register
Ar20			M		Reserved
Ar21		FCR	M	Preserved	IA-32 floating-point control registers
Ar22 Ar23			M		Reserved
Ar24		EFLAG	M	Preserved	IA-32 EFLAG register
Ar25	ar.csd	CSD	M	Scratch	Compare and store data register; IA-32 code segment descriptor
Ar26	ar.ssd	SSD	M	Scratch	IA-32 stack segment descriptor
Ar27		CFLG	M	Preserved	IA-32 combined CR0 and CR4 register
Ar28		FSR	M	Preserved	IA-32 floating-point status register
Ar29		FIR	M	Preserved	IA-32 floating-point instruction register
Ar30		FDR	M	Preserved	IA-32 floating-point data register
Ar31			M		Reserved
Ar32	ar.ccv		M	Scratch	Compare and exchange "compare value" register
Ar33 Ar35			M		Reserved
Ar36	ar.unat		M	According to Gr class	User NaT collection register
Ar37 Ar39			M		Reserved
Ar40	ar.fpsr		M	Preserved	Floating-point status register
Ar41 Ar43			M		Reserved
Ar44	ar.itc		M	Read-only	Interval time counter
Ar45 Ar47			M		Reserved
Ar48 Ar63			M, I		Ignored
Ar64	ar.pfs		I	Special	Previous function state
Ar65	ar.lc		I	Preserved	Loop count register
Ar66	ar.ec		I	Automatic	Epilog count register
Ar67 Ar111			I		Reserved
Ar112 Ar127			M, I		Ignored