A small, fast memory area that holds recently used instructions and data
Decode unit
A component that controls access to the address and data buses
Execution unit
A component that breaks an instruction into its constituent parts
Control unit
A small number of memory locations used by the control and execution units to store data temporarily
Registers
A register that stores recently taken branches to aid in branch prediction
L1 cache
A component that performs the actual data processing, such as adding and subtracting
Branch target buffer
A holding place for instructions and operands that a processor will need
Bus interface unit
A component that acts as a scheduler for the execution units
3:
Put the following steps in order to describe how a processor handles input:
Executes instruction
Writes data
Fetches instruction
Transfers data
Decodes instruction
4:
Match the technology with its description:
Pipelined
A processor that does not wait for one instruction to be completed before it begins another
Superscalar
A processor with an expanded number of steps that it uses to complete an instruction
Hyper-pipelined
A processor that can execute more than one instruction per clock cycle
Branch prediction
A processor in which the compiler tells the execution units which instructions can be processed in parallel
Out-of-order execution
A technology in which the first time a branch instruction is executed, its address and that of the correct branch are stored in the branch target buffer
EPIC
A processor technology that can process instructions first that do not depend on another instruction
5:
Match the technology with its description:
Asymmetric multiprocessing
All processors share all memory.
Symmetric multiprocessing
The next task is executed on the next available processor.
Loosely coupled
Tasks are assigned to specific processors.
Tightly coupled
Each processor has memory assigned to it and, in a sense, acts as an independent computer.
6:
When mixing processors, to which processor core frequency should the core frequency of each processor be set?
7:
Which processor should be installed as the bootstrap processor?
