The reference transconductor was simulated to confirm its signal handling and the filter design was simulated to confirm its amplitude response, noise performance, signal handling, intermodulation distortion and
Under typical conditions, the single-ended transconductor (Figure 5.17) used
Figure 5.19:
Simulated differential transconductance of 20
μ
S transconductor
The amplitude responses and
Figure 5.20:
Simulated amplitude response
Figure 5.21:
Simulated passband response and group delay
Figure 5.22:
Simulated passband response without feedthrough equalisation
The 1 dB compression point occurred with a differential output swing of 1.3 V peak to peak (at 1 MHz), but the maximum differential voltage swing was restricted to 1 V peak to peak, corresponding to the maximum wanted Bluetooth signal of
−
20 dBm and required an input current swing of 40
μ
A peak to peak. Figure 5.23 shows an output NPSD in the passband of aproximately 90 nV/
√
. The signal-to-noise ratio, found by comparing the power of the maximum signal with that of the noise integrated over 100 MHz bandwidth, was 68.2 dB.
Figure 5.23:
Simulated output noise spectral density
For the IM3 test, sinusoids at 4 MHz and 7 MHz with amplitudes 2 dB below the maximum signal were applied and the resulting simulated output spectrum is shown in Figure 5.24. The third-order product at 1 MHz was at a level of − 86 dBV and this gives an IIP3 of 34.2 dBV.
Figure 5.24:
Simulated third-order intermodulation
For the supply noise intermodulation test, first
V
dd
and then
V
ss
were modulated by a 1.5 MHz sinusoid while the input was driven with a 0.5 MHz sinusoid, each with amplitudes of 100 mV peak. These signals were both
Figure 5.25:
Simulated power supply-signal intermodulation
The total current drain for the whole Gm-C filter was 512
μ
A giving a power consumption of approximately 1 mW. The estimated chip area (including automatic tuning) is approximately 0.18 mm
2
. The results with nominal processing, at
|
|
|
Process |
2.5 V, 0.25 μ m CMOS (C050FM) |
||
|---|---|---|---|
|
|
|||
|
Filter shape |
Chebyshev |
||
|
Filter order |
5 + 5 |
||
|
Filter ripple |
0.5 dB |
||
|
Supply voltage ( V dd ) |
2 V |
||
|
|
|||
|
Temperature |
− 20 °C |
27 °C |
80 °C |
|
|
|||
|
Analogue supply( V dda ) |
1.568 V |
1.580 V |
1.607 V |
|
Supply current ( I dd ) |
410 μ A |
512 μ A |
641 μ A |
|
Centre frequency ( F ) |
1.036 MHz |
1.000 MHz |
0.952 MHz |
|
Bandwidth ( F bw ) |
1.241 MHz |
1.200 MHz |
1.143 MHz |
|
Gain ( A ) |
− 6.05 dB |
− 6.13 dB |
− 6.27 dB |
|
Signal/noise (SNR) |
68.6 dB |
68.2 dB |
67.9 dB |
|
IIP3 (4 MHz, 7 MHz) |
33.9 dBV |
34.2 dBV |
30.8 dBV |
|
Supply intermodulation (0.5 MHz, 1.5 MHz) |
− 45.6dB |
− 47.7dB |
− 50.8dB |
|
|
|||
|
Estimated chip area (filter) |
≈ 0.1mm 2 |
||
|
|
|||
|
Estimated chip area (tuning) |
≈ 0.08 mm 2 |
||
|
|
With the transconductors deliberately skewed to emulate a 20 per cent mismatch between the transconductor's pMOS and nMOS transistors (the pMOS transistors were made 10 per cent wider and the nMOS transistors 10 per cent narrower), there were only minor changes to the typical performance as shown in Table 5.3. This justifies our claim that matching between the pMOS and nMOS
|
|
|
Transconductance ratio ( k p / k n ) |
1.0 |
1.2 |
|---|---|---|
|
|
||
|
Transconductor |
||
|
Supply voltage ( V dd ) |
2V |
2V |
|
Supply voltage ( V dda ) |
1.580 V |
1.586 V |
|
Quiescent input voltage ( V in ) |
0.756 V |
0.770 V |
|
Transconductance ( G ) |
39.93 μ S |
40.57 μ S |
|
Channel Filter |
||
|
Centre frequency |
1.000 MHz |
1.014 MHz |
|
Bandwidth |
1.200 MHz |
1.217 MHz |
|
Passband gain |
− 6.13 dB |
− 6.27 dB |
|
Signal/noise ratio |
68.2 dB |
68.2 dB |
|
IIP3 (4 MHz, 7 MHz) |
34.2 dBV |
33.1 dBV |
|
Supply intermodulation (0.5 MHz, 1.5 MHz) |
− 47.7dB |
− 47.7dB |
|
Supply current ( I dd ) |
512 μ A |
532 μ A |
|
Power dissipation |
1.024 mW |
1.064 mW |
|
|
Figure 5.26 shows the tuning loop (Figure 5.16) settling from start-up under typical conditions. It can be seen that the loop stabilises with the charge pump enable input,
e
n
, oscillating around 1 V and with its output,
Q
out
,
Figure 5.26:
Simulated start-up behaviour of the tuning loop (see Figure 5.16)
Figure 5.27:
Simulated
V
dda
ripple of the tuning loop