2.3 Classes of Instruction Set Architectures

Computer instruction sets vary greatly from machine to machine. We can usefully classify instruction sets into several categories based on the number of addresses contained within the typical instruction.

Perhaps simplest would be a computer with a zero-address, or stack-based, instruction set. Part of the processor state for such a machine includes a pointer to the top of a last-in first-out (LIFO) list, or stack, which may reside either in memory or in special storage within the processor. The stack pointer is an implicit operand for most instructions; it is not explicitly specified in the instruction word. On such a machine, the instructions

 PUSH      A POP       B 

cause the contents of memory location A to be placed on the top of the stack (as a result of the PUSH); the contents of the stack are then removed and copied into memory location B (as a result of the POP). Arithmetic instructions always operate on the top one or two elements of the stack, depending on whether they are unary or binary operations. For example, the instruction

 ADD 

adds the top two elements of the stack together, popping those elements from the stack and then pushing the resultant sum onto the top of the stack. Such machines are called zero-address machines because arithmetic operations such as ADD have no explicit operands; the operands are implicitly known to be the top two stack elements. Some hand-held calculators behave like zero-address computing devices.

A computer with a one-address instruction set typically has a single register, usually called the accumulator. Just as the stack is an implied operand for instructions on a stack machine, the single accumulator is the implied operand for a one-address machine. We could add the contents of memory locations A and B, putting the result in location C, on a one-address machine using a program fragment such as the following:

 LOAD      A ADD       B STORE     C 

The LOAD instruction copies the contents of memory location A into the accumulator. Then the ADD instruction finds and adds the contents of location B to the accumulator. Finally, the STORE instruction copies the contents of the accumulator into memory location C. In this architecture, it is not possible to add a number directly to the contents of a memory location; the summation must be formed in a processor register. The Digital PDP-8 architecture used one-address instructions.

A two-address instruction set allows two operands to be specified for the instruction. For example,

 ADD      A, B 

adds the contents of location A to the contents of location B. When the instruction is completed, the contents of location A are unchanged while location B now contains the sum. In some architectures the semantic order of the operands would be reversed, with the result of A := A + B instead of B := A + B. Here we have cited the operand semantics of the IA-32 and Digital Equipment Corporation architectures.

Finally, a three-address instruction set allows two source operands and one destination operand to be specified in the instruction. For example,

 ADD      A, B, C 

adds the contents of location A to the contents of location B and stores the result of the summation in a third location. When the instruction is completed, the contents of locations A and B are unchanged while location C now contains the sum. Again, we have cited the operand semantics of the IA-32 and Digital Equipment Corporation architectures.

These are just some of the options available to the designer of an instruction set, and several may be included in a given machine architecture. For example, the VAX provided for both the two- and the three-address ADD instructions just illustrated, while the PDP-11 only provided for the two-address version. In general, the more operands an instruction set allows, the more powerful the instructions tend to become. Yet as the instruction set becomes more powerful in this way, the hardware required to implement the complete instruction set also becomes more complex. For this reason, contemporary architectures tend to have no more than three operands for most of their instructions.

Like several RISC designs, the Itanium architecture describes a two-address machine with respect to load and store operations, which are the only instruction types that may reference the contents of memory. In such instructions, one address refers to a memory location and the other to a processor register. Other Itanium instructions typically involve three or more addresses.