2.4 Migration to 64-Bit Architectures

A strategy for retaining the existing customer base typically accompanies any major change of architecture in the computer industry. IBM had that concern when two not-so-similar lines, System/36^™ and System/38^™, were going to be supplanted by the AS/400^® line. A combination of hardware and software emulation strategies made that transition rather successful.

When Digital Equipment Corporation introduced the 32-bit VAX line, the first few implementations contained hardware emulation of the instruction set of the 16-bit PDP-11 line. Later VAX implementations omitted those hardware features, substituting PDP-11 software emulation.

A mixed approach was taken toward assistance for the existing customer base with the advent of Alpha-based systems. The Alpha architecture natively supported the IEEE floating-point standard, but also supported certain VAX-specific legacy representations in hardware. For other elements of the VAX architecture, powerful software tools were furnished with Alpha operating systems that could translate VAX application binaries.

New architectures typically evolve from and within a single manufacturer, growing from elements of existing ISA families or drawing upon internal research and development. The Itanium architecture brings together two major and distinct companies and their architectural assets. Hewlett-Packard brings to the architecture a natural evolution of the 32- and 64-bit RISC principles and instruction styles from its existing PA-RISC architecture, developed over two decades. Intel's skill in designing highly complex digital hardware capable of operating at extremely high clock rates has made possible the incorporation of HP's RISC designs into a new ISA with a high degree of internal parallelism.

Hewlett-Packard's customers are accustomed to high-performance workstations and servers that run the Unix-based operating system HP-UX^®. Current implementations of Itanium processors allow those customers to continue to operate their current applications with little more than a minor revision of the operating system and the utilization of dynamic application migration tools known collectively as Aries. For these users, Itanium architecture represents a rather smooth transition and an opportunity to plan new high-performance applications that take advantage of EPIC principles.

For Intel, and thus for a significant portion of the computer industry, the 64-bit Itanium architecture represents a change, a challenge, and an opportunity. The IA-32 architecture, as represented by the Pentium^® family, differs more sharply from Itanium architecture than, say, VAX architecture differed from Alpha architecture. Moreover, the affected customer base end users and vendors is enormous and disparate. To smooth the transition for all customers, particularly those that create application software and operating systems, the first Itanium processors include on-chip the hardware equivalent of a Pentium III processor. This implementation is expected to facilitate the transition from 32- to 64-bit computing for the largest computing customer base in history.

Most contemporary CPU chips are superscalar machines containing several functional units. These may include one or more units specially designed to execute various subsets of the instruction set. That is, the CPU as a whole may be able to load data from memory, perform an arithmetic operation on integers, and multiply two floating-point quantities all at the same time. As a corollary, several instructions may need to be fetched simultaneously in order to keep those functional units doing productive work.

Itanium instructions differ from most in that their width is 41 bits and every three instructions are bundled with an additional 5-bit code specifying the ways in which that trio of instructions either can or cannot execute truly simultaneously with one another and with instructions in following bundles.

In this book, we first devise programs emphasizing the RISC-like features of the Itanium instruction set architecture. Then gradually we discuss the additional power of its EPIC aspects, and demonstrate how explicit parallelism and predication demand that compilers do more work to attain efficient system performance.

Virtual addresses within the Itanium architecture are potentially 64 bits wide, though the specification permits the physical address space of an implementation to be as small as 44 bits. Since address bits are used to specify 8-bit bytes, the Itanium architecture expects a byte-addressable memory system. Memory access occurs in binary multiples of bytes. In particular, instruction bundles have a total width of 128 bits (16 bytes). Furthermore, performance is substantially hindered unless memory access can proceed with uniformly aligned data; in particular, instruction bundles must be aligned according to addresses having the lowest-order bits as 0000.