Summary

Computations for applications in science and engineering require the flexibility of scaling that floating-point representations provide. High-performance workstations and servers marketed, in part, for such applications usually incorporate support for floating-point operations.

RISC designs typically depart from the CISC tradition of one set of universal registers and instead provide a dedicated set of floating-point registers in a major section of the CPU devoted to IEEE floating-point operations. Partitioning of the CPU into floating-point and integer units can lead to performance gains of at least two sorts. First, the separate units can be designed with different depths of pipelining appropriate to the operations carried out by each. Second, the strict "division of labor" makes possible the simultaneous execution of floating-point instructions and integer instructions if a compiler interleaves them.

In this chapter, we have discussed the Itanium instructions that involve the floating-point register set, with an emphasis on double-precision forms. Distinctive aspects of the Itanium approach include: an 82-bit register representation that supports extended bits in the exponent field; both floating-point and integer forms of fused multiply add instructions that work with 64-bit significands; numerous types of format conversions and merge operations; fast hardware approximations of the reciprocal and the reciprocal square root that can be refined to full-precision reciprocals, quotients, remainders, and square roots by highly optimized software sequences; versatile floating-point compare instructions that set Itanium predicate registers; and floating-point logical instructions that can perform bitwise editing of the 64-bit significand field in the register representation.

We included in this chapter two programming examples, one brief and the other extended, that used several types of instructions and that introduced simple ways to inspect a floating-point result using a debugger or the C printf function.



ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ISBN: N/A
EAN: N/A
Year: 2003
Pages: 223

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