Basic characteristics of SPARC assembly language

There are some essential characteristics of SPARC instructions that come from the fact that the system is a RISC, Reduced Instruction Set Computer, architecture. Whereas some computer designs attempt to provide many instructions to do complex tasks , RISC machines are designed to be simple (at least in hardware), providing fewer but faster instructions. One consequence of this is that it may take more, sometimes many more, instructions to accomplish the same task that one CISC, Complex Instruction Set Computer, instruction would do.

For example, on a CISC processor, we might be able to execute one instruction to increment the current value stored in memory location 4000. Using a RISC processor, we might need to perform three instructions.

1. Read the contents of location 4000 into a register.

2. Increment the value stored in the register.

3. Write the value stored in the register back to location 4000.

However, the RISC machine can usually perform the longer sequence of code more quickly, getting the job done as fast or faster than the CISC machine.

While the RISC architecture may make life easier for hardware designers, compiler writers often bang their heads on walls trying to generate efficient code. However, since this is not a book for compiler hackers, we will concentrate on what you might encounter during debugging when looking at generated code: common instructions, common sequences, and common failings. We will be talking about the Version 8 specification for the SPARC chip. This is a 32-bit implementation; in other words, a full word is 32 bits wide. (Version 7 is quite similar, but lacks a few instructions. It is still a 32-bit specification, and Version 7 code runs fine on a Version 8 processor.)

Since the SPARC is a "simpler" machine, you will find some tradeoffs when it's compared to a CISC architecture. A potentially large instruction set was compressed into fewer, more frequently used commands, which can be executed very quickly. This means many common instructions appear to be missing. However, life is not all bad. One feature of the RISC architecture is that there are lots of registers to play with. These all hold one full word (32 bits) of information. Instructions, as much as possible, deal directly with these registers rather than going to memory for their data each time. This scheme provides some dramatic increases in speed of execution.

Registers contain the data for almost all instructions. Any arithmetic instruction, logical operation, or testing is done with all the values in registers. Parameters to functions and function return values are also set up in registers rather than being pushed onto the stack. Of course, there are a limited number of registers, and any parameters left over do have to be put someplace, so they are, in fact, stuffed onto the stack. But, as you'll see, it's much more expensive in terms of time and instruction space to access these values, or any data in memory, so as much as possible is done using the registers alone.

Data in memory is accessible as bytes (signed or unsigned), short 16-bit words (also signed or unsigned), long words (a full 32 bits), or double-words. There are some severe restrictions on where data can be placed, however. Short words must be stored on a 2-byte boundary (in other words, the address of a short must be even). A full word needs to go on a 4-byte boundary. And, reasonably enough, a double-word must have an address divisible by 8. If an instruction tries to access data in memory with a badly aligned address, this attempt will result in an immediate Address Alignment Trap , and the instruction will fail. When this happens in the kernel, the system panics, reporting a bad trap.