4.11 The Standard Multichannel Interface (MADI)

4.11 The Standard Multichannel Interface (MADI)

Originally proposed in the UK in 1988 by four manufacturers of professional audio equipment (Sony, Neve, Mitsubishi and Solid State Logic), the so-called 'MADI' interface is now an AES and ANSI standard. It was designed to simplify cabling in large installations, especially between multitrack recorders and mixers, and has a lot in common with the format of the two-channel interface. The standard concerned is AES10-1991 12 (ANSI S4.43-1991), and a recent draft revision has been issued. This interface was intentionally designed to be transparent to standard two-channel data making the incorporation of two-channel signals into a MADI multiplex a relatively straightforward matter. The original channel status, user and auxiliary data remain intact within the multichannel format.

MADI stands for Multichannel Audio Digital Interface; in the original standard 56 channels of audio are transferred serially in asynchronous form and consequently the data rate is much higher than that of the two-channel interface. For this reason the data is transmitted either over a coaxial transmission line with 75 ohm termination (not more than 50 m) or over a fibre optic link. The protocol is based closely on the FDDI (Fibre-Distributed Digital Interface) protocol suggesting that fibre optics would be a natural next step 34 . The recent draft revision proposes a means of allowing higher sampling frequencies and an extension of the channel capacity.

4.11.1 Format of the Multichannel Interface

The serial data structure is as shown in Figure 4.25. It is divided into subframes which, apart from the preamble area, are identical to AES3 subframes. The preamble is not required here because the interface is synchronized in a different way, so the four-bit slot is replaced with four 'mode bits' the functions of which are labelled in the diagram. There are 56 subframes in a frame and bit 0 signifies the start of channel 0 (it is set true for that frame only); bit 1 indicates whether a particular subframe or audio channel is active (1 for active); bit 2 indicates whether the subframe is either the A or B channel of a two-channel pair derived from an AES3 source (1 for 'B'); and bit 3 indicates the start of a new channel status block for the channel concerned. The audio part of the frame is handled in the same way as in the two-channel interface, and the V, U, C and P bits apply on a per-channel basis, with parity applying over bits 431.

image from book
Figure 4.25: Format of the MADI frame.

The channel code is different from that used in the two-channel version, and another important contrast is that the link transmission rate is independent of the audio sampling frequency or number of channels involved. In the original standard the highest data transfer rate is at the highest sampling rate (54 kHz) and number of channels (56) times the number of bits per subframe (32), that is 54000 — 56 — 32 = 96.768 Mbit/s. It is assumed that the transmitter and receiver will be independently synchronized to a common sampling frequency reference in order that they operate at identical sampling frequencies. In the recent draft revision sampling frequencies up to 96kHz are allowed and the maximum channel capacity is extended to 64 by limiting the sampling frequency to no more than 48 kHz (removing the varispeed tolerance in other words). Samples of 96 kHz are handled by reducing the channel capacity to 28 and by either using an approach similar to the AES3 single-channel-doublesampling-frequency mode described earlier, or by transmitting two sets of samples successively within one 20.8 s frame.

The MADI link itself does not synchronize the receiver's sampling clock. The channel-coding process involves two stages: first the 32-bit subframe is divided into groups of 4 bits, and these groups are then encoded into 5-bit words chosen to minimize the DC content of the data signal, according to Table 4.10 (4/5-bit encoding).

Table 4.10: 4/5-bit encoding in MADI

4-bit groups

5-bit codes

































The actual transmission rate of the data is thus 25% higher than the original data rate, and 32-bit subframes are transmitted as 40 bits. To carry the 4/5-encoded data over the link a '1' is represented by a transition (in either direction) and a '0' by no transition, as shown in the example of Figure 4.26.

image from book
Figure 4.26: An example of the NRZI channel code.

Special synchronization symbols are inserted by the transmitter in between encoded subframes, and these take the binary form 11000 10001, transmitted from the left (a pattern which does not arise otherwise ). These have the function of synchronizing the receiver (but not its sample clock) and may be inserted between subframes or at the end of the frame in order to fill the total data capacity of the link which is 125Mb/s 100ppm. The prototype MADI interfaces were designed around AMD's TAXI (Transparent Asynchronous Xmitter/Receiver interface) chips, which were becoming more widely used in high speed computer networks, and these chips normally take care of the insertion of synchronizing symbols so that the transmission rate of the link remains constant.

4.11.2 Electrical Characteristics

The coaxial version of the interface consists of a 75 ohm transmission line terminated in BNC connectors, using cable with a characteristic impedance of 75 2 ohms and losses of <0.1dB/m (1100MHz). Suggested driver and receiver circuits are illustrated in the standard, and the receiver is expected to decode data with a minimum eye pattern as shown in Figure 4.27. Equalization is not permitted at the receiver, and distances of up to 50 metres may be covered.

image from book
Figure 4.27: The minimum eye pattern acceptable for correct decoding of MADI data.

The block diagram of transmitter-to-receiver communication is shown in Figure 4.28. Here the source data is buffered, 4/5 encoded and then formatted with the sync symbols before being transmitted. The receiver extracts the sync symbols, decodes the 4/5 symbols and a buffer handles any short- term variation in timing due to the asynchronous nature of the interface. An external sync reference ensures that the two sampling clocks are locked.

image from book
Figure 4.28: Block diagram of MADI transmission and reception .

Digital Interface Handbook
Digital Interface Handbook, Third Edition
ISBN: 0240519094
EAN: 2147483647
Year: 2004
Pages: 120
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